Datasheet

255
32117D–AVR-01/12
AT32UC3C
15.3.4 Debug Operation
When an external debugger forces the CPU into debug mode, the FLASHC continues normal
operation. If the FLASHC is configured in a way that requires it to be periodically serviced by the
CPU through interrupts or similar, improper operation or data loss may result during debugging.
15.4 Functional description
15.4.1 Bus Interfaces
The FLASHC has two bus interfaces, one High-Speed Bus (HSB) interface for reads from the
flash memory and writes to the page buffer, and one Peripheral Bus (PB) interface for issuing
commands and reading status from the controller.
15.4.2 Memory Organization
The flash memory is divided into a set of pages. A page is the basic unit addressed when pro-
gramming the flash. A page consists of several words. The pages are grouped into 16 regions of
equal size. Each of these regions can be locked by a dedicated fuse bit, protecting it from acci-
dental modification.
• p pages (FLASH_P)
•w bytes in each page and in the page buffer (FLASH_W)
• pw bytes in total (FLASH_PW)
• f general-purpose fuse bits (FLASH_F), used as region lock bits and for other device-specific
purposes
• 1 security fuse bit
• 1 Factory Page
• 1 User Page
15.4.3 User Page
The User page is an additional page, outside the regular flash array, that can be used to store
various data, such as calibration data and serial numbers. This page is not erased by regular
chip erase. The User page can only be written and erased by a special set of commands. Read
accesses to the User page are performed just as any other read accesses to the flash. The
address map of the User page is given in Figure 15-1.
15.4.4 Factory page
The Factory page is an additional page, outside the regular flash array, that can be used to store
various data, such as calibration data and serial numbers. This page is not erased by regular
chip erase. Read accesses to the Factory page is performed just as any other read access to the
flash. The address map of the Factory page is given in Figure 15-1.
15.4.5 Read Operations
The on-chip flash memory is typically used for storing instructions to be executed by the CPU.
The CPU will address instructions using the HSB bus, and the FLASHC will access the flash
memory and return the addressed 32-bit word.
In systems where the HSB clock period is slower than the access time of the flash memory, the
FLASHC can operate in 0 wait state mode, and output one 32-bit word on the bus per clock
cycle. If the clock frequency allows, the user should use 0 wait state mode, because this gives
the highest performance as no stall cycles are encountered.