Datasheet

247
32117D–AVR-01/12
AT32UC3C
14.7.16 Overrun Interrupt Mask Register
Name: OVIMR0 - OVIMR1
Access Type: Read-only
Offset: 0x0D0 - 0x0D4
Reset Value: 0x00000000
• OVIM: Overrun Interrupt Mask
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
This bit is cleared when the corresponding bit in OVIDR is written to one.
This bit is set when the corresponding bit in OVIER is written to one.
Note:
Channels 0 to 31 are controlled by OVIMR0.
Channels 32 to 63 are controlled by OVIMR1.
Please refer to the Module Configuration section at the end of this Chapter for device-specific channel mapping information.
31 30 29 28 27 26 25 24
OVIM
23 22 21 20 19 18 17 16
OVIM
15 14 13 12 11 10 9 8
OVIM
76543210
OVIM