Datasheet

244
32117D–AVR-01/12
AT32UC3C
14.7.13 Trigger Interrupt Disable Register
Name: TRIDR0 - TRIDR1
Access Type: Write-only
Offset: 0x0A0 - 0x0A4
Reset Value: -
• TRID: Trigger Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding bit in IMR.
Note:
Channels 0 to 31 are controlled by TRIDR0.
Channels 32 to 63 are controlled by TRIDR1.
Please refer to the Module Configuration section at the end of this Chapter for device-specific channel mapping information.
31 30 29 28 27 26 25 24
TRID
23 22 21 20 19 18 17 16
TRID
15 14 13 12 11 10 9 8
TRID
76543210
TRID