Datasheet

243
32117D–AVR-01/12
AT32UC3C
14.7.12 Trigger Interrupt Enable Register
Name: TRIER0 - TRIER1
Access Type: Write-only
Offset: 0x090 - 0x094
Reset Value: -
• TRIE: Trigger Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the corresponding bit in TRIMR.
Note:
Channels 0 to 31 are controlled by TRIER0.
Channels 32 to 63 are controlled by TRIER1.
Please refer to the Module Configuration section at the end of this Chapter for device-specific channel mapping information.
31 30 29 28 27 26 25 24
TRIE
23 22 21 20 19 18 17 16
TRIE
15 14 13 12 11 10 9 8
TRIE
76543210
TRIE