Datasheet

241
32117D–AVR-01/12
AT32UC3C
14.7.10 Trigger Status Clear Register
Name: TRSCR0 - TRSCR1
Access Type: Write-only
Offset: 0x070 - 0x074
Reset Value: -
• TRSC: Trigger Interrupt Status Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding bit in TRSR.
Note:
Channels 0 to 31 are controlled by TRSCR0.
Channels 32 to 63 are controlled by TRSCR1.
Please refer to the Module Configuration section at the end of this Chapter for device-specific channel mapping information.
31 30 29 28 27 26 25 24
TRSC
23 22 21 20 19 18 17 16
TRSC
15 14 13 12 11 10 9 8
TRSC
76543210
TRSC