Datasheet

240
32117D–AVR-01/12
AT32UC3C
14.7.9 Trigger Status Register
Name: TRSR0 - TRSR1
Access Type: Read-only
Offset: 0x060 - 0x064
Reset Value: 0x00000000
• TRS: Trigger Interrupt Status
0: An interrupt event has not occurred
1: An interrupt event has occurred
This bit is cleared by writing a one to the corresponding bit in TRSCR.
Note:
Channels 0 to 31 are controlled by TRSR0.
Channels 32 to 63 are controlled by TRSR1.
Please refer to the Module Configuration section at the end of this Chapter for device-specific channel mapping information.
31 30 29 28 27 26 25 24
TRS
23 22 21 20 19 18 17 16
TRS
15 14 13 12 11 10 9 8
TRS
76543210
TRS