Datasheet

236
32117D–AVR-01/12
AT32UC3C
14.7.5 Channel Enable Register
Name: CHER0 - CHER1
Access Type: Write-only
Offset: 0x020 - 0x024
Reset Value: -
• CHE: Channel Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the corresponding bit in CHSR.
Note:
Channels 0 to 31 are controlled by CHER0.
Channels 32 to 63 are controlled by CHER1.
Please refer to the Module Configuration section at the end of this Chapter for device-specific channel mapping information.
31 30 29 28 27 26 25 24
CHE
23 22 21 20 19 18 17 16
CHE
15 14 13 12 11 10 9 8
CHE
76543210
CHE