Datasheet

235
32117D–AVR-01/12
AT32UC3C
14.7.4 Channel Status Register
Name: CHSR0 - CHSR1
Access Type: Read-only
Offset: 0x010 - 0x014
Reset Value: 0x00000000
• CHS: Channel Status
0: The corresponding channel is disabled.
1: The corresponding channel is enabled.
This bit is cleared when the corresponding bit in CHDR is written to one.
This bit is set when the corresponding bit in CHER is written to one.
Note:
Channels 0 to 31 are controlled by CHSR0.
Channels 32 to 63 are controlled by CHSR1.
Please refer to the Module Configuration section at the end of this Chapter for device-specific channel mapping information.
31 30 29 28 27 26 25 24
CHS
23 22 21 20 19 18 17 16
CHS
15 14 13 12 11 10 9 8
CHS
76543210
CHS