Datasheet

224

32117D–AVR-01/12

AT32UC3C

13.7 Module Configuration

The specific configuration for each FREQM instance is listed in the following tables. The module

bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-

ager chapter for details.

Table 13-2. Module Clock Name

Module Name Clock Name Description

FREQM

CLK_FREQM Peripheral Bus clock from the PBA clock domain

CLK_MSR Measured clock

CLK_REF Reference clock

Table 13-3. Register Reset Values

VERSION 0x00000310

Table 13-4. Clock Sources for CLK_MSR

CLKS

EL Clock/Oscillator Description

0 CLK_CPU The clock the CPU runs on

1 CLK_HSB High Speed Bus clock

2 CLK_PBA Peripheral Bus A clock

3 CLK_PBB Peripheral Bus B clock

4 CLK_PBC Peripheral Bus C clock

5 OSC0 Output clock from Oscillator 0

6 OSC1 Output clock from Oscillator 1

7 OSC32K Output clock from OSC32K

8 RCSYS Output clock from RCSYS Oscillator

9 RC8M Output clock from 8MHz / 1MHz RC Oscillator

13-24 GCLK0-11 Generic clock 0 through 11

25 RC120M Output clock from RC120M

26-31 Reserved

Table 13-5. Clock Sources for CLK_REF

REFSEL Clock/Oscillator Description

0 RCSYS System 115 KHz RC oscillator clock

1 OSC32K Output clock from OSC32K

2 OSC0 Output clock from Oscillator 0