Datasheet

183
32117D–AVR-01/12
AT32UC3C
11.7 Interrupt Request Signal Map
The various modules may output Interrupt request signals. These signals are routed to the Inter-
rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64
groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt
signals in the same group share the same autovector address and priority level. Refer to the
documentation for the individual submodules for a description of the semantics of the different
interrupt requests.
The interrupt request signals are connected to the INTC as follows.
Table 11-2. Interrupt Request Signal Map
Group Line Module Signal
0 0 AVR32UC3 CPU
SYSBLOCK
COMPARE
1
0 AVR32UC3 CPU OCD DCEMU DIRTY
1 AVR32UC3 CPU OCD DCCPU READ
2 0 Secure Access Unit SAU
3
0 Peripheral DMA Controller PDCA 0
1 Peripheral DMA Controller PDCA 1
2 Peripheral DMA Controller PDCA 2
3 Peripheral DMA Controller PDCA 3
4
0 Peripheral DMA Controller PDCA 4
1 Peripheral DMA Controller PDCA 5
2 Peripheral DMA Controller PDCA 6
3 Peripheral DMA Controller PDCA 7
5
0 Peripheral DMA Controller PDCA 8
1 Peripheral DMA Controller PDCA 9
2 Peripheral DMA Controller PDCA 10
3 Peripheral DMA Controller PDCA 11
6
0 Peripheral DMA Controller PDCA 12
1 Peripheral DMA Controller PDCA 13
2 Peripheral DMA Controller PDCA 14
3 Peripheral DMA Controller PDCA 15
7 0 Memory DMA MDMA
8 0 USB 2.0 OTG Interface USBC