Datasheet
1247
32117D–AVR-01/12
AT32UC3C
39.7 Module Configuration
The bit mapping of the Peripheral Debug Register (PDBG) is described in the following table.
Please refer to the On-Chip Debug chapter in the AVR32UC Technical Reference Manual for
details.
Table 39-59. Bit mapping of the Peripheral Debug Register (PDBG)
bit Peripheral
0 AST
1WDT
2CANIF
3 QDEC0
4 QDEC1
5ADCIFA
6ACIFA0
7ACIFA1
8DACIFB0
9DACIFB1
10 PEVC
11-31 Reserved