Datasheet

119
32117D–AVR-01/12
AT32UC3C
8.6.21 Generic Clock Control
Name: GCCTRL
Access Type: Read/Write
Offset: 0x0064-0x008C
Reset Value: 0x00000000
There is one GCCTRL register per generic clock in the device.
• DIV: Division Factor
• OSCSEL: Oscillator Select
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
DIV
15 14 13 12 11 10 9 8
OSCSEL
76543210
------DIVENCEN
Table 8-12. Generic Clock Source
OSCSEL Clock Description
0 RCSYS System RC oscillator clock
1 OSC32K Output clock from OSC32K
2 8MHz / 1MHz RCOSC Output clock from RC8M
3 OSC0 out Output clock from Oscillator 0
4 OSC1 out Output clock from Oscillator 1
5 PLL0 out Output from PLL 0
6 PLL1 out Output from PLL 1
7 CPU clock The clock the CPU runs on
8 HSB clock High Speed Bus clock
9 PBA clock Peripheral Bus A clock
10 PBB clock Peripheral Bus B clock
11 PBC clock Peripheral Bus C clock
12-15 Reserved