Datasheet

1158
32117D–AVR-01/12
AT32UC3C
• DSE: DAC Data Setup Extra Clock Cycle
0: No extra clock latency.
1: Add an extra clock cycle latency between data written and start of conversion. This may be useful when the DAC clock is
running fast. Adding an extra clock cycle latency might help meeting the data setup time constraint.
• DDA: DAC Dual Data in Data Register A
0:No dual data in DR0.
1:Dual data in DR0. This allows writing two 16-bit wide data words in a single write operation to the DR0 register. In this case the
16 upper bits are assigned to the channel B data word while the lower 16 bits remain assigned to the channel A data word.
• LP: DAC Low Power Reduction Mode
0: DAC low power mode disabled.
1: DAC low power mode enabled.