Datasheet

1157
32117D–AVR-01/12
AT32UC3C
37.7.2 Configuration Register
Name:
CFR
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
• CHC: DAC Channel Configuration
These bits control whether the DAC should operate with sample and hold on outputs or not.
• ABE: DAC Auto Triggered Mode Enable Channel B
0: The conversion is triggered by the data register write access.
1: the incoming event (from the event line selected in the ECR Register) triggers the conversion.
• AAE: DAC Auto Triggered Mode Enable Channel A
0: The conversion is triggered by the data register write access.
1: the incoming event (from the event line selected in the ECR Register) triggers the conversion.
• REF: DAC Reference Selection
This bit controls the voltage reference selection and therefore the output voltage range of the DAC.
31 30 29 28 27 26 25 24
------ CHC
23 22 21 20 19 18 17 16
- - - - - - ABE AAE
15 14 13 12 11 10 9 8
-------REF
76543210
-----DSEDDALP
CHC Description
00 S/H modules on both channels are deactivated. Internal routing only.
01 Single channel operation: conversions on channel A only (S/H module activated).
10 Single channel operation: conversions on channel B only (S/H module activated).
11 Dual channel operation: conversions on both channels with both S/H modules activated.
REF Voltage Reference Selection
0 External Reference (VREF+ pin)
1VDDANA