Datasheet

1154
32117D–AVR-01/12
AT32UC3C
V
DACxX
= gain x (DATA
CHx
/ 0xFFF) + offset
In an ideal DAC, gain is 1 and offset 0.
37.6.3 Interrupts
An interrupt request will be generated if the corresponding bit in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared
by writing a one to the corresponding bit in the Status Clear Register (SCR).
After processing a channel input data, if the data input buffer is empty, the DACIFB signals a
data empty interrupt to the interrupt controller.
An underrun interrupt will be generated if two consecutive trigger events are issued without any
new channel data being fed to the DACIFB in the meantime.
An overrun interrupt will be generated if an additional channel data is sent to the DACIFB while
the input buffer is already full.
37.6.4 Peripheral Events
Channel conversions can be triggered by an independent event source. A simple arbiter priori-
tizes trigger event requests if the two channels are activated at the same time.
Trigger events for both channels are taken either from the PEVC input or from the DACIFB inter-
nal trigger timers. These two timers are set up separately and both use PrescalerClock as their
reference clock (see the TRA and TRB registers).