Datasheet

1149
32117D–AVR-01/12
AT32UC3C
37.3 Block Diagram
Figure 37-1. DACIFB Block Diagram
Analog DAC
DAC INTERFACE (DACIFB)
Data Channel A
Data Channel B
DAC Channel A
S/H Output
DAC Channel B
S/H Output
DAC CTRL
Data
Alignment
DAC
Output Control
and Driver
(S/H)
Channel B
Trigger MUX
Enable
A/B Select
Data Alignment
16 bits
16 bits
Trig select B
P
B
I/O
Controller
Trig select A
Arbiter
DAC CALIBRATION
CTRL
Gain Calibration
Offset Calibration
Ch B
12 bits
Ch A
12 bits
P
D
C
A
Timer
Channel A
Timer
Channel B
Channel A
Trigger MUX
Peripheral Event
Controller (PEVC)
I
N
T
C
O
N
T
R
O
L
Prescaler
Ch A data empty
Internal Output to
Analog Comparator or
ADC
Ch B data empty
Ch A data underrun
Ch B data underrun
Ch A data overrun
Ch B data overrun