Datasheet

1146
32117D–AVR-01/12
AT32UC3C
36.8 Module configuration
The specific configuration for each ADC instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks according to the table in the Sys-
tem Bus Clock Connections section.
The differential inputs of the ADC are configured through the following registers of the ADCIFA:
• INPSEL00, INPSEL01, INNSEL00 and INNSEL01 for the sequencer 0
• INPSEL10, INPSEL11, INNSEL10 and INNSEL11 for the sequencer 1
The configuration allows to select pin or internal voltage.
The ADC voltage reference can be selected as external reference through the RS register of the
ADCIFA.
For detail, see the ADCIFA chapter.
Table 36-13. Module configuration
Feature ADCIFA
NBCONV 8
Table 36-14. Module clock name
Module name Clock name Description
ADCIFA CLK_ADCIFA Peripheral Bus clock from the PBC clock domain
Table 36-15. Register Reset Values
Register Reset Value
VERSION 0x00000110
PARAMETER 0X00000808