Datasheet

1135
32117D–AVR-01/12
AT32UC3C
36.7.13 Internal Timer Register
Name:
ITIMER
Access Type: Read/Write
Offset: 0x48
Reset Value: 0x00000000
• ITMC: Internal Timer Max Counter
Number of ADC clock cycles to wait for is (ITMC + 1).
note: This allows SOC period up to 167 ms when CkADC clock is running at 1.5 MHz.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
-------ITMC[16]
15 14 13 12 11 10 9 8
ITMC[15:8]
76543210
ITMC[7:0]