Datasheet

1118
32117D–AVR-01/12
AT32UC3C
36.6.18 Arbitration
In dual sequencer mode, SEQ0 has priority over SEQ 1. Due to the ADC pipeline topology, the
arbiter is implemented in order to allocate optimal time slots to each sequencer in order to pipe
requests. When all analog voltages have been taken into account in the ADC pipeline, an other
sequencer can drive the analog blocs without waiting for the end of the whole conversion pro-
cess. The ADC result will be sampled by another process when getting the wanted precision.
36.6.19 Interrupts
Table 36-11.
ADCIFA Interrupt Group
Line Line Description Related Status
0 Sequencer 0
Sequencer 0 end of sequence
Sequencer 0 end of conversion
Sequencer 0 overrun
Sequencer 0 (last converted value) overrun
Sequencer 0 missed start-of-conversion
1 Sequencer 1
Sequencer 1 end of sequence
Sequencer 1 end of conversion
Sequencer 1 overrun
Sequencer 1 (last converted value) overrun
Sequencer 1 missed start-of-conversion
2 Start-up done Start-up done
3 Window
Window 0
Window 1