Datasheet

1117
32117D–AVR-01/12
AT32UC3C
36.6.16 Calibration
Accuracy of the conversion is based on calibration of switched capacitors and operational ampli-
fiers offset cancellation. Gain correction is done by writing a calibration word into the ADCCAL
and SHCAL registers since it is temperature and operating voltage independent.
36.6.16.1 ADC gain error calibration
The ADC is gain-calibrated during production, but to take advantage of this the calibration value
must be read from the factory page in flash and written to the Gain Calibration (GCAL) field of
the ADCCAL register.
36.6.16.2 ADC offset error calibration
Offset cancellation has to be performed by the user due to temperature and operating voltage
conditions dependence. The offset can be obtained by converting a null differential value. That
offset has to be negated and written into the Offset Calibration (OCAL) field of the ADCCAL reg-
ister. Then, for each conversion result, the controller will return the converted value added with
the signed OCAL value. For instance, if the offset value obtained is 0x3, then the value 0xFD
must be written to OCAL. Please note that OCAL is a 6 bits register, if the MSB is high then the
value will be considered negative. A saturation mechanism avoids flipping phenomena. OCAL
stores a signed number of LSB assuming the calibration has been performed in 12 bits resolu-
tion. If converting at a lower resolution, correction will only take into account the appropriate
most significant bits.
36.6.16.3 Sample and hold gain error calibration
S/H are gain-calibrated during production, but to take advantage of this the calibration value
must be read from the factory page in flash and written to the Sample and Hold Gain Calibration
(GAIN0 and GAIN1) fields of the SHCAL register.
36.6.17 Window Monitor
There are 2 window monitors that allow to compare two of the result registers to some pre-
defined threshold values. The Window Mode (WM) field in WCFGy register (see Table 36-10)
allows the user to configure operating mode in order to generate interrupts. The High Threshold
(HT) and Low Threshold (LT) fields in WCFGy register give the threshold voltage values of the
comparators. The result register to monitor is selected by the Source (SRC) field in WCFGy
register.
Note: Comparisons are performed regardless with the HWLA setting (half word left adjust).
Table 36-10. Window Modes
WM Modes
0 0 0 No window mode (default)
0 0 1 Mode 1: active when result < HT
0 1 0 Mode 2: active when result > LT
0 1 1 Mode 3: active when LT < result < HT
1 0 0 Mode 4: active when result >= LT or result >= HT
101reserved
110reserved
111reserved