Datasheet

1115
32117D–AVR-01/12
AT32UC3C
36.6.10 Analog Reference
The following sources are available as analog reference (AREF) in the ADC. They are selected
through the Reference Source (RS) field in the CFG register:
• 1V internal voltage reference
• 0.6*VDDANA internal voltage reference
• Two external reference voltage (ADCREF0 or ADCREF1 over chip analog ground)
When using an internal reference, it is recommended inserting a decoupling capacitor between
ADCREFP and ADCREFN externally (mandatory to get the full 12-bits precision). This means
that two pins will be dedicated to reference decoupling. If the pins are needed for other pur-
poses, the decoupling may be skipped giving a conversion accuracy of 10 bits.
It is also possible to force a differential reference by setting the CFG.EXREF bit. This will bypass
the CFG.RS selection setting and make the ADC use the differential ADCREFP/ADCREFN pin
pair voltage as reference.
36.6.11 Conversion Range
The conversion amplitude range is given by the ADC acquisition mode and the reference
source:
36.6.12 Conversion Results
If the Half Word Left Adjust (HWLA) bit in the SEQCFGx register is set, then the result will be left
adjusted on the 16 lower bits of the RESn register. Otherwise, results will be right-adjusted. The
offset error can be digitally compensated using the ADCCAL.OCAL field. For more information
refer to Section 36.6.16.2 ”ADC offset error calibration” on page 1117.
ADC transfer function:
Given the ISSTRICTNEG(x) function defined below
ISSTRICTNEG(x) = 0 when x>0 or x=0
ISSTRICTNEG(x) = 1 when x<0
All conversion results are signed in two's complement representation. Extra bits depending on
resolution and left adjust settings are padded with the sign bit. It means that if you read RESn
registers as a 32 bits register, the result will be correct.
Table 36-8. Conversion Range vs. Reference
Reference Conversion range
Internal reference 1 ±1V
Internal reference 2 ±0.6 * VDDANA
External reference 1 ± min(3.5 V, VDDANA - 0.7)
External reference 2 ± min(3.5 V, VDDANA - 0.7)
RESn
GAIN V ADCIN p() VADCINn()()–()()×
V VREFP()V VREFN()–()
---------------------------------------------------------------------------------------------------------
2
SRES 1– HWLA 16 SRES–()×+
× ISSTRICTNEG V ADCIN p) VADCINn()()–()()()– OCAL+=