Datasheet

1113
32117D–AVR-01/12
AT32UC3C
36.6.8.1 Dynamic mode
Dynamic mode aims at improving conversion accuracy when performing channel sweeping or
measures on high frequency input signals. It is then recommended using the SHDYN (sample
and hold dynamic mode) bit control in the SEQCFGx register. Doing this causes the insertion of
a supplementary sampling cycle of one CkADC clock period used to reset the sample and hold.
As a consequence, conversion rate is divided by two. Please note that it is useless performing
oversampling when using that mode since the S/H are reseted before actually sampling.
Figure 36-9. SH Dynamic Mode
36.6.8.2 Gain factor
S/H allows the amplification of very small signals or buffering of very high impedance signal
sources. The gain factor may be configured from 1x to 64x by writing to the Sequencer Conver-
sion n Sample and Hold Gain (GCNVn) field of the SHGx register. The gain can be changed
from sample to sample by writing the SHGx registers.
Table 36-7. Gain Factor
GCNVn Gain
0001
0012
0104
0118
10016
10132
11064
111Reserved