Datasheet

1108
32117D–AVR-01/12
AT32UC3C
Figure 36-2. Single Sequencer Chronogram (assuming SRES=8, SHD=0)
36.6.4.3 Dual-sequencer mode (simultaneous sampling)
The ADC has the ability to sample two pairs of ADCINx inputs simultaneously (see Figure 36-3),
provided that one pair is from the inputs available on the sequencer 0 and the other is from the
inputs available on the sequencer 1 (see Figure 36-1). To put the ADC into simultaneous sam-
pling mode, the SSMQ bit needs to be clear in the CFG register.
Figure 36-3. Dual Sequencer Chronogram (assuming SRES=8, SHD=0)
In this chronogram, ADCCONV signal represents the value being sampled by the ADC
36.6.4.4 Sequencer behavior on a Start Of Conversion
Thanks to the SOCB bit in the SEQCFGx register, 2 different sequencer behaviors are possible:
Table 36-5. SOCB Behavior
SOCB Comment
0 All sequence conversions are performed on a SOC event.
1 A single conversion belonging to the sequence is performed on a SOC event.