Datasheet

1106
32117D–AVR-01/12
AT32UC3C
36.5.6 Debug Operation
When an external debugger forces the CPU into debug mode:
• the ADCIFA continues normal operation if the bit related to ADCIFA in PDBG register is ‘0’.
PDCA access continues normal operation and may interfere with debug operation.
• the ADCIFA is frozen if the bit related to ADCIFA in PDBG register is ‘1’. When the ADCIFA is
frozen, ADCIFA PB registers can still be accessed. Then, reading registers may modify
status bits (OVRx, LOVRx) like in normal operation. PDCA access are pending.
36.6 Functional Description
36.6.1 ADC Resolution
The ADC supports 8-bit, 10-bit or 12 bits resolutions. Precision can be set differently for each
sequencer by setting the SRES bits in the SEQCFGx register. By default, after a reset, the reso-
lution is set to 12 bits. To get full resolution, the user should first calibrate the ADC as detailed in
Section 36.6.16.
36.6.2 ADC Conversion Modes
36.6.2.1 Differential / single ended
The ADC is fully differential. To perform single ended measures, the user can perform pseudo
unipolar conversions by connecting ground onto the negative input. User can connect it to an
external ground through pads or internal ground depending on if there's one connected onto the
negative input multiplexer. Since conversion results are always 12 bits in 2's complement repre-
sentation, the sign bit will not change, and then the resulting resolution is 11 bits max.
36.6.2.2 S/H versus DIRECT conversions
By default S/H are enabled, to change that setting, set the Sample and Hold disable bit (SHD)
located in the CFG register. Maximum accuracy is achieved when disabling S/H but setting this
bit forbids dual sequencer mode, Sequencer 1 is then switched off. Furthermore, in this mode
S/H are switched off to lower power consumption.
Table 36-2. S/H versus DIRECT Conversions
Mode Characteristics
S/H
Pros
Gain setting (1, 2, 4, 8, 16, 32, 64)
Dual sequencer mode
Cons
Reduced accuracy
Dynamic limitation (fixed with over-sampling)
1 ADC clock period spent to propagate into S/H
DIRECT
Pros
No dynamic limitation due to S/H
Full accuracy
Saves 1 ADC clock period compared to the features list timings
Cons
No gain
Single sequencer mode only