Datasheet

1105
32117D–AVR-01/12
AT32UC3C
36.4 I/O Lines Description
36.5 Product Dependencies
36.5.1 I/O Lines
The pins used for interfacing the ADCIFA may be multiplexed with the I/O Controller lines. The
programmer must first program the I/O Controller to assign the desired ADCIFA pins to their
peripheral function. If I/O lines of the ADCIFA are not used by the application, they can be used
for other purposes by the I/O Controller.
Not all ADCIFA inputs may be enabled. If an application requires only four channels, then only
four ADCIFA lines need to be assigned to ADCIFA inputs.
36.5.2 Power Management
If the CPU enters a sleep mode that disables clocks used by the ADCIFA, the ADCIFA will stop
functioning and resume operation after the system wakes up from sleep mode. Before entering a
sleep mode where the clock to the ADCIFA is stopped, make sure the Analog-to-Digital Con-
verter cell is put in an inactive state. Refer to Section 36.6.3 for more information.
36.5.3 Clocks
The clock for the ADCIFA bus interface (CLK_ADICFA) is generated by the Power Manager.
This clock is turned on by default, and can be enabled and disabled in the Power Manager. It is
recommended to disable the ADCIFA before disabling the clock, to avoid freezing the ADCIFA in
an undefined state.
36.5.4 Interrupts
The ADCIFA interrupt line is connected to one of the internal sources of the Interrupt Controller
(INTC). Using the ADCIFA requires the INTC to be configured first.
36.5.5 Event System
The event controller provides the ADCIFA two trigger sources.
Table 36-1. I/O Lines Description
Name Description
ADCINx ADC analog input
ADCREFP
CFG.EXREF= 0: Normal operation, this pin is used to decouple ADC internal reference.
ADCREFP should be connected to a 100nF external decoupling capacitor.
CFG.EXREF= 1: Forcing reference using ADCREFP/ADCREFN differential pin pair voltage
Please refer to the Section 36.6.10 for more information.
ADCREFN
CFG.EXREF= 0: Normal operation, this pin is used to decouple ADC internal reference.
ADCREFN should be connected to a 100nF external decoupling capacitor.
CFG.EXREF= 1: Forcing reference using ADCREFP/ADCREFN differential pin pair voltage
Please refer to the Section 36.6.10 for more information.
ADCREF0 External reference input (with respect to analog ground) bypassed when CFG.RS is enabled
ADCREF1 External reference input (with respect to analog ground) bypassed when CFG.RS is enabled
VDDANA Analog power supply
GNDANA Analog ground