Datasheet

1102
32117D–AVR-01/12
AT32UC3C
36. ADC Interface (ADCIFA)
Rev. 1.1.0.4
36.1 Features
• 8/10/12-bit ADC core with built-in dual sample and hold (S/H)
• 16 channels
• Up to 1.5 mega-samples per second conversion rate for 12 bits resolution
– Conversion time near to 5.3µs (12 bits resolution at 1.5 Msps)
• Up to 2 mega-samples per second conversion for lower resolution
– Conversion time near to 3.5µs (10 bits resolution at 2 Msps)
– Conversion time near to 3µs (8 bits resolution at 2 Msps)
• Multiple reference sources
– 1V internal voltage reference
– 0.6 * VDDANA internal
– Two external reference voltage
• Direct measures or sampled with sample-and-hold
• Sample-and-hold (S/H) acquisition time window has separate prescale control (gain: 1, 2, 4, 8, 16,
32, 64).
• Sequencer can be operated as two independent 8-state sequencers operating on its own S/H
(dual sequencer mode) or as one large 16-state sequencer (single sequencer mode)
• 16 result registers
• Source selection for the start-of-conversion (SOC)
– Software
– Embedded timer
– Peripheral Event Controller
– Continuous
• Two sequencer modes:
– Run the whole sequence on a start-of-conversion
– Run a single conversion on a start-of-conversion
• Flexible interrupt control allows interrupt request on every end-of-sequence or on every single
conversion.
• Windowing mechanism, with selectable channel
• Free running mode
• 2 PDCA channels (one per sequencer)
• Power reduction modes
• Programmable ADC timings