Datasheet

1073
32117D–AVR-01/12
AT32UC3C
34.8 Module Configuration
The specific configuration for each QDEC instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
Table 34-3. QDEC Clock Name
Module Name Clock Name Description
QDEC0 CLK_QDEC0 Peripheral Bus clock from the PBA clock domain
GCLK_QDEC0 The generic clock used for the QDEC0 is GCLK5
QDEC1 CLK_QDEC1 Peripheral Bus clock from the PBA clock domain
GCLK_QDEC1 The generic clock used for the QDEC1 is GCLK6
Table 34-4. Register Reset Values
Register Reset Value
VERSION 0x00000100
PARAMETER 0x000000FF