Datasheet

1065
32117D–AVR-01/12
AT32UC3C
34.7.7 Status Register
Name:
SR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x00000000
• CLKEN: QDEC Counter Clock Status
This bit is cleared when the QDEC and CLK_QDEC_INT has been disabled
This bit is set when the QDEC and CLK_QDEC_INT has been enabled
• CNTDIR: Counter Direction
This bit is cleared when the counter counts up
This bit is set when the counter counts down
• TRIGGER: Trigger Event Occurrence
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the trigger event has occurred
• QDERR: Illegal Quadrature Signals Transition
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when an illegal transition of quadrature signals has occurred
• OVR: Overrun Capture
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the overrun capture event has occurred
• DIRINV: Count Direction Inversion
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the count direction has changed
• IDXERR: Index Error
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when an index error has occurred
• RCRO: Revolution Counter Roll Over
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the revolution counter has rolled over
• PCRO: Position Counter Roll Over
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the position counter has rolled over
31 30 29 28 27 26 25 24
- –––––––
23 22 21 20 19 18 17 16
------CLKENCNTDIR
15 14 13 12 11 10 9 8
------TRIGGERQDERR
76543210
OVR DIRINV IDXERR RCRO PCRO CAP CMP QEPI