Datasheet

1059
32117D–AVR-01/12
AT32UC3C
34.7.2 Configuration Register
Name:
CF
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
• UPD: Up/Down Timer Mode
0: Up/Down functionality in Timer Mode is disabled
1: Up/Down functionality in Timer Mode is ensabled
• TSDIR: Timer Set Direction
0: The counters count up in Timer Mode
1: The counters count down in Timer Mode
The count direction is updated when a trigger (software or hardware) occurs
• FILTEN: Input Digital Filter Enable
0: The input digital filter is disabled
1: The input digital filter is enabled
• IDXPHS: QEPI Detection Phase
0: QEPI detection enabled when QEPA signal equals 0 and QEPB signal equals 0
1: QEPI detection enabled when QEPA signal equals 0 and QEPB signal equals 1
2: QEPI detection enabled when QEPA signal equals 1 and QEPB signal equals 0
3: QEPI detection enabled when QEPA signal equals 1 and QEPB signal equals 1
• IDXINV: QEPI Phase
0: QEPI will not be inverted
1: QEPI will be inverted
• PHSINVB: QEPB Phase
0: QEPB will not be inverted
1: QEPB will be inverted
• PHSINVA: QEPA Phase
0: QEPA will not be inverted
1: QEPA will be inverted
• EVTRGE: Event Trigger Enable
0: The event trigger function is disabled
1: The event trigger function is enabled
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
------UPDTSDIR
15 14 13 12 11 10 9 8
- - FILTEN IDXPHS IDXINV PHSINVB PHSINVA
76543210
- - - EVTRGE RCCE PCCE IDXE QDEC