Datasheet

1056
32117D–AVR-01/12
AT32UC3C
• The RCRO interrupt to detect a roll-over of the revolution counter.
• The IDXERR interrupt to detect that the index signal (QEPI) is detected and the position
counter does not have the expected value (TOP.PCTOP if the counter counts up, 1 if the
counter counts down).
• The DIRINV interrupt occurs when the count direction changes.
• The QDERR interrupt occurs when a bad transition in the quadrature signals is detected (for
example, from “00” to “11”). This could be caused by erroneous programming of the
GCLK_QDEC frequency.
• The TRIGGER interrupt occurs when a trigger event from PEVC is detected. It could be used
by software to detect a reset of the counters.
•
Each interrupt source can be enabled by writing a one to the corresponding bit in the Interrupt
Enable Register (IER) and disabled by writing a one to the corresponding bit in the Interrupt Dis-
able Register (IDR). The enable status can be read from the Interrupt Mask Register (IMR). The
status of the interrupt sources, even if the interrupt is masked, can be read in SR. When an inter-
rupt has occurred, it is reset by writing a one to the corresponding bit in the Status Clear
Register (SCR).
34.6.4 Peripheral Events
The QDEC can receive three peripheral events from the Peripheral Event Controller (PEVC):
• The trigger peripheral event starts CLK_QDEC_INT and enables the counter.
• The capture peripheral event captures CNT in the Capture register (CAP).
• The toggle_dir peripheral event toggles the count direction when the QDEC works in Timer
mode with UPD mode active.
The QDEC can send one event to the PEVC:
• The compare peripheral event when the CNT register reaches the Compare register (CMP)
value.
The PEVC must be programmed to enable QDEC peripheral events.