Datasheet

1054
32117D–AVR-01/12
AT32UC3C
34.6.2.2 Capture register
The capture function saves the QDEC counter value in the Capture register (CAP) when a cap-
ture event has occurred. The capture function is enabled if the QDEC counter is running.
The CAP register will not be updated with a new value if the previous value has not been read. If
a capture event occurs and the previous value has not been read, the SR.OVR bit is set.
34.6.2.3 Glitch filter
The QDEC inputs (QEPA/QEPB/QEPI) are passed through a glitch filter that is enabled by writ-
ing a one to the CF.FILTEN bit. The input sent to the QDEC counter will toggle if the input is
stable for three CLK_QDEC_INT periods.
34.6.2.4 Timer/Counter mode
QDEC can be used as a 32-bit/counter with compare/capture capabilities. This timer includes an
up/down (UPD) mode where the timer counts up or down according to a toggle direction event
from the PEVC.
The timer/counter is available by writing a zero to the CF.QDEC bit. Timer/Counter mode uses
the same resources as QDEC mode:
• The CNT QDEC counter
• The TOP register to reload the CNT value
• The CMP register to generate a compare peripheral event/interrupt
• The CAP register to save the CNT value in case of a capture peripheral event occurs
• The clock selection
• The trigger mechanism
It does not use the input filters and the index pulse control.
The timer/counter includes an up/down mode that is enabled by writing a one to the CF.UPD bit.