Datasheet

1053
32117D–AVR-01/12
AT32UC3C
Figure 34-6. PC reset by QEPI signal (TOP.PCTOP = 79, CF.IDXPHS =”00”, CF.IDXE = “1”)
34.6.1.8 Quadrature frequency
The CLK_QDEC clock frequency must be at least two times the QEPA and QEPB frequency as
these signals are synchronized to the CLK_QDEC clock. To get the maximum available fre-
quency on QEPA/QEPB signals, the filter on inputs should be bypassed.
For a 33 MHz peripheral bus clock the maximum QEPA frequency is 16.5 MHz. For a wheel with
8192 lines the maximum rotational speed supported by QDEC is 16.5MHz / 8192 = 2014 rps =
120 849 rpm.
34.6.1.9 Disabling the QDEC
The QDEC is disabled by writing a zero to CTRL.CLKEN.
34.6.2 Advanced Operation
34.6.2.1 Compare register
The Compare register (CMP) is used to generate an interrupt and a peripheral event when the
CNT register reaches the value defined in CMP.
If RC compare is enabled (CF.RCCE is one), a compare match occurs when RC is equal to
RCCMP. A peripheral event is generated and the CMP interrupt line is set if enabled.
If the PC compare is enabled (CF.PCCE is one), a compare match occurs when the PC is equal
to PCCMP. A peripheral event is generated and the CMP interrupt line is set if enabled.
If both RC compare and PC compare are enabled, a compare match occurs when CNT is equal
to CMP. A peripheral event is generated and the CMP interrupt line is set if enabled.
The compare peripheral event should be mapped through the PEVC to another peripheral.
QEPA
QEPB
QPulse
QEPI
72 7473 75 0 1 2 3 2 1 0 79 78
PC
010
RC
77
IDXERR