Datasheet

1051
32117D–AVR-01/12
AT32UC3C
Figure 34-3. Clock Control
34.6.1.2 Trigger
A trigger resets the QDEC counter and starts CLK_QDEC_INT. Two triggers are possible:
• A software trigger, by writing a one to the Software Trigger bit in CTRL
(CTRL.SWTRG).
• Trigger peripheral event from the PEVC: If enabled by writing a one to the Event
Trigger Enable bit in the Configuration Register (CF.EVTRGE).
The QDEC counter is reset when the peripheral trigger event occurs.
34.6.1.3 Quadrature decoder logic and digital filter
The quadrature decoder logic converts the 2-phase signals QEPA and QEPB in a count pulse
signal (QPulse) for each transition and a DIR signal to indicate the rotation direction.
Figure 34-4. Quadrature Description
The QEPI signal may be used to detect a reference position once per revolution.
The 3 inputs (QEPA/QEPB/QEPI) can be inverted by writing to appropriate bits in CF.
CLK_QDEC_INT
PEVC trigger
CTRL[CLKEN]= 1
A
N
D
Set
Reset
CTRL[CLKEN]=0
GCLK_QDEC
A
N
D
SR[CLKEN]
Q
QEPA
QEPB
(0,0)
(0,1)
(1,1)
(1,0)
{A,B} =
01
00
10
11
Decrement
counter
Decrement
counter
Decrement
counter
Decrement
counter
Increment
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Increment
counter
Increment
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Increment
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