Datasheet

1049
32117D–AVR-01/12
AT32UC3C
34.3 Block Diagram
Figure 34-2. QDEC Block Diagram
34.4 I/O Lines Description
34.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
34.5.1 I/O Lines
The QDEC pins are multiplexed with other peripherals. The user must first program the I/O Con-
troller to give control of the pins to the QDEC.
quadrature
decoder
CNT =
position counter/
revolution counter
CAP
register
CMP
register
QEPA
QEPB
QEPI
QPulse
DIR
PB
compare event
capture event
trigger event
Filter
Filter
Filter
QCF.FILTEN
Clock
Control
TOP register
CLK_QDEC_INT
Advanced
filter
GCLK_QDEC
Table 34-1. I/O Lines Description
Pin Name Pin Description Type
QEPA Quadrature phase signal A Input
QEPB Quadrature phase signal B Input
QEPI Quadrature index signal Input