Datasheet

1047
32117D–AVR-01/12
AT32UC3C
33.8 Module Configuration
The specific configuration for each PWM instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
33.8.1 PWM fault sources
The following table define the mapping of the PWM fault sources. For details on PWM faults, see
Fault Protection paragraph in the PWM chapter.
Table 33-8. PWM Clock Name
Module name Clock Name Description
PWM CLK_PWM Peripheral Bus clock from the PBA clock domain
GCLK The generic clock used for the PWM is GCLK4
Table 33-9. Register Reset Values
Register Reset Value
VERSION 0x00000501
Table 33-10. PWM fault sources
fault input number Description
0 PEVC channel output 8, this fault is only usable when the FMR.FMODy is set
to 1.
1 PEVC channel output 9, this fault is only usable when the FMR.FMODy is set
to 1.
2 EXT_FAULTS[0] input pin, See Peripheral Multiplexing on I/O line chapter.
3 EXT_FAULTS[1] input pin, See Peripheral Multiplexing on I/O line chapter.
4 clock failure detector of PM, See PM chapter for details.