Datasheet

1042
32117D–AVR-01/12
AT32UC3C
33.7.41 Channel Period Update Register
Name:
CPRDUPD
Access Type: Write-only
Offset: 0x210 + [ch_num * 0x20]
Reset Value: -
This register can only be written if the WPSWS3 and WPHWS3 bits are cleared in ”Write Protect Status Register” on page
1030.
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the
waveform period.
Only the first 20 bits (channel counter size) are significant.
• CPRDUPD: Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
– By using the PWM internal clock (CCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
– By using the PWM internal clock (CCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
– By using the PWM internal clock (CCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
31 30 29 28 27 26 25 24
- -------
23 22 21 20 19 18 17 16
CPRDUPD
15 14 13 12 11 10 9 8
CPRDUPD
76543210
CPRDUPD
X CPRDUPD×()
CCK
--------------------------------------------
CRPDUPD DIVA×()
CCK
------------------------------------------------------- -
CRPDUPD DIVB×()
CCK
------------------------------------------------------- -