Datasheet

1021
32117D–AVR-01/12
AT32UC3C
33.7.23 Fault Mode Register
Name:
FMR
Access Type: Read/Write
Offset: 0x05C
Reset Value: 0x00000000
This register can only be written if the WPSWS5 and WPHWS5 bits are cleared in ”Write Protect Status Register” on page
1030.
• FFILy: Fault y Filtering
0: The fault input y is not filtered.
1: The fault input y is filtered.
• FMODy: Fault y Activation Mode
0: The fault y is active as long as the fault input x is at FPOLy.
1: The fault y becomes active as soon as the fault input y is at FPOLy level. The fault y stays active until the fault input y is not at
FPOLy level AND until it is cleared in ”Fault Clear Register” on page 1023.
• FPOLy: Fault y Polarity
0: The fault y becomes active when the fault input y is set to 0.
1: The fault y becomes active when the fault input y is set to 1.
CAUTION: To prevent an unexpected activation of the FSy bit in the ”Fault Status ReSister” on page 1022, the FMODy bit
can be set to one only if the FPOLy bit has been previously configured to its final value.
31 30 29 28 27 26 25 24
- -------
23 22 21 20 19 18 17 16
FFIL7 FFIL6 FFIL5 FFIL4 FFIL3 FFIL2 FFIL1 FFIL0
15 14 13 12 11 10 9 8
FMOD7 FMOD6 FMOD5 FMOD4 FMOD3 FMOD2 FMOD1 FMOD0
76543210
FPOL7 FPOL6 FPOL5 FPOL4 FPOL3 FPOL2 FPOL1 FPOL0