Datasheet

102
32117D–AVR-01/12
AT32UC3C
• PLLOSC: PLL Oscillator Select
0: Oscillator 0 is the source for the PLL.
1: Oscillator 1 is the source for the PLL.
2: 8MHz/1MHz RCOSC is the source for the PLL.
3: Reserved.
• PLLEN: PLL Enable
0: PLL is disabled.
1: PLL is enabled.
Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please
refer to the UNLOCK register description for details.
Table 8-4. PLLOPT Fields Description
Description
PLLOPT[0]: VCO frequency
080MHz<f
vco
<180MHz
1 160MHz<f
vco
<240MHz
PLLOPT[1]: Output divider
0f
PLL
= f
vco
1f
PLL
= f
vco
/2
PLLOPT[2]
0 Wide Bandwidth Mode enabled
1 Wide Bandwidth Mode disabled