Datasheet

1006
32117D–AVR-01/12
AT32UC3C
33.7.9 Sync Channels Mode Register
Name:
SCM
Access Type: Read/Write
Offset: 0x020
Reset Value: 0x00000000
This register can only be written if the WPSWS2 and WPHWS2 bits are cleared in ”Write Protect Status Register” on page
1030.
• PTRCS: PDCA Transfer Request Comparison Selection
Selection of the comparison used to set the WRDY bit and the corresponding PDCA transfer request.
• PTRM: PDCA Transfer Request Mode
• UPDM: Synchronous Channels Update Mode
0: Manual write of double buffer registers and manual update of synchronous channels. The update occurs at the beginning of
the next PWM period, when the UPDULOCK bit in ”Sync Channels Update Control Register” on page 1008 is set.
1: Manual write of double buffer registers and automatic update of synchronous channels. The update occurs when the Update
Period is elapsed.
2: Automatic write of duty-cycle update registers by the PDCA and automatic update of synchronous channels. The update
occurs when the Update Period is elapsed.
3: Reserved.
31 30 29 28 27 26 25 24
- -------
23 22 21 20 19 18 17 16
PTRCS PTRM - - UPDM
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – SYNC3 SYNC2 SYNC1 SYNC0
Table 33-6. WRDY bit and PDCA Transfer Request
UPDM PTRM WRDY bit and PDCA Transfer Request
0x
The WRDY bit in ”Interrupt Status Register 2” on page 1014 and the PDCA transfer request are
never set to 1.
1x
The WRDY bit in ”Interrupt Status Register 2” on page 1014 is set to 1 as soon as the update
period is elapsed, the PDCA transfer is never requested.
2
0
The WRDY bit in ”Interrupt Status Register 2” on page 1014 and the PDCA transfer is requested
as soon as the update period is elapsed.
1
The WRDY bit in ”Interrupt Status Register 2” on page 1014 and the PDCA transfer is requested
as soon as the selected comparison matches.