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Features

• High Performance, Low Power 32-bit AVR

Microcontroller

– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set

– Built-in Floating-Point Processing Unit (FPU)

– Read-Modify-Write Instructions and Atomic Bit Manipulation

– Performing 1.49 DMIPS / MHz

• Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State)

• Up to 49 DMIPS Running at 33 MHz from Flash (0 Wait-State)

– Memory Protection Unit

• Multi-hierarchy Bus System

– High-Performance Data Transfers on Separate Buses for Increased Performance

– 16 Peripheral DMA Channels Improves Speed for Peripheral Communication

• Internal High-Speed Flash

– 512 Kbytes, 256 Kbytes, 128 Kbytes, 64 Kbytes Versions

– Single Cycle Access up to 33 MHz

–FlashVault

™

Technology Allows Pre-programmed Secure Library Support for End

User Applications

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

• Internal High-Speed SRAM, Single-Cycle Access at Full Speed

– 64 Kbytes (512 KB and 256 KB Flash), 32 Kbytes (128 KB Flash), 16 Kbytes (64 KB

Flash)

– 4 Kbytes on the Multi-Layer Bus System (HSB RAM)

• External Memory Interface on AT32UC3C0 Derivatives

– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)

• Interrupt Controller

– Autovectored Low Latency Interrupt Service with Programmable Priority

• System Functions

– Power and Clock Manager

– Internal 115KHz (RCSYS) and 8MHz/1MHz (RC8M) RC Oscillators

– One 32 KHz and Two Multipurpose Oscillators

– Clock Failure detection

– Two Phase-Lock-Loop (PLL) allowing Independent CPU Frequency from USB or

CAN Frequency

• Windowed Watchdog Timer (WDT)

• Asynchronous Timer (AST) with Real-Time Clock Capability

– Counter or Calendar Mode Supported

• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency

• Ethernet MAC 10/100 Mbps interface

– 802.3 Ethernet Media Access Controller

– Supports Media Independent Interface (MII) and Reduced MII (RMII)

• Universal Serial Bus (USB)

– Device 2.0 and Embedded Host Low Speed and Full Speed

– Flexible End-Point Configuration and Management with Dedicated DMA Channels

– On-chip Transceivers Including Pull-Ups

• One 2-channel Controller Area Network (CAN)

– CAN2A and CAN2B protocol compliant, with high-level mailbox system

– Two independent channels, 16 Message Objects per Channel

32117D–AVR–01/12

32-bit AVR

Microcontroller

AT32UC3C0512C

AT32UC3C0256C

AT32UC3C0128C

AT32UC3C064C

AT32UC3C1512C

AT32UC3C1256C

AT32UC3C1128C

AT32UC3C164C

AT32UC3C2512C

AT32UC3C2256C

AT32UC3C2128C

AT32UC3C264C

Summary of content (1316 pages)

PAGE 1
Features • High Performance, Low Power 32-bit AVR® Microcontroller – – – – • • • • • • • • • • • • Compact Single-cycle RISC Instruction Set Including DSP Instruction Set Built-in Floating-Point Processing Unit (FPU) Read-Modify-Write Instructions and Atomic Bit Manipulation Performing 1.
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AT32UC3C • One 4-Channel 20-bit Pulse Width Modulation Controller (PWM) • • • • • • • • • • • • • • – Complementary outputs, with Dead Time Insertion – Output Override and Fault Protection Two Quadrature Decoders One 16-channel 12-bit Pipelined Analog-To-Digital Converter (ADC) – Dual Sample and Hold Capability Allowing 2 Synchronous Conversions – Single-Ended and Differential Channels, Window Function Two 12-bit Digital-To-Analog Converters (DAC), with Dual Output Sample System Four Analog Compara
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AT32UC3C 1. Description The AT32UC3C is a complete System-On-Chip microcontroller based on the AVR32UC RISC processor running at frequencies up to 66 MHz. AVR32UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance.
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AT32UC3C The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module provides on-chip solutions for network-connected devices.
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AT32UC3C 2. Overview Block diagram Block diagram TDO TCK TDI TMS AVR32UC CPU JTAG INTERFACE NEXUS CLASS 2+ OCD MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N VBUS D+ DID VBOF USB INTERFACE M Flash Controller 512/ 256/ 128/64 KB Flash M S S M W M R M S M M PBB HSB PB S CONFIGURATION PERIPHERAL DMA CONTROLLER S REGISTERS HSB Memory DMA COL, CRS, RXD[3..0], RX_CLK, RX_DV, RX_ER, TX_CLK DMA BUS HSB PB HSB-PB BRIDGE B HSB-PB BRIDGE A DATA[15..0] ADDR[23..0] NCS[3..
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AT32UC3C 2.2 Configuration Summary Table 2-1.
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AT32UC3C Table 2-1.
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AT32UC3C 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Table 3-1 on page 11. QFN64/TQFP64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PD01 PD00 PC22 PC21 PC20 PC19 PC18 PC17 PC16 PC15 PC05 PC04 GNDIO2 VDDIO2 PC03 PC02 Figure 3-1.
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AT32UC3C TQFP100 Pinout 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PD01 PD00 PC31 PC24 PC23 PC22 PC21 PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12 PC11 PC07 PC06 PC05 PC04 GNDIO2 VDDIO2 PC03 PC02 Figure 3-2.
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AT32UC3C LQFP144 Pinout 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PD01 PD00 PC31 PC30 GNDIO3 VDDIO3 PC29 PC28 PC27 PC26 PC25 PC24 PC23 PC22 PC21 PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12 PC11 PC10 PC09 PC08 PC07 PC06 PC05 PC04 GNDIO2 VDDIO2 PC03 PC02 Figure 3-3.
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AT32UC3C 3.2 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1.
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AT32UC3C Table 3-1.
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AT32UC3C Table 3-1.
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AT32UC3C Table 3-1.
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AT32UC3C Table 3-1.
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AT32UC3C Table 3-1.
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AT32UC3C Table 3-2. 3.2.3 Peripheral Functions Function Description aWire DATAOUT aWire output in two-pin mode JTAG port connections JTAG debug port Oscillators OSC0, OSC32 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-3.
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AT32UC3C depending on the configuration of the OCD AXS register. For details, see the AVR32UC Technical Reference Manual. Table 3-5. 3.2.
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AT32UC3C Table 3-7. Signal Description List Signal Name Active Level Function Type 1.8V Voltage Regulator Input Power Input Power Supply: 4.5V to 5.5V or 3.0V to 3.6 V VDDIN_33 USB I/O power supply Power Output/ Input Capacitor Connection for the 3.3V voltage regulator or power supply: 3.0V to 3.6 V VDDCORE 1.8V Voltage Regulator Output Power output Capacitor Connection for the 1.
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AT32UC3C Table 3-7.
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AT32UC3C Table 3-7.
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AT32UC3C Table 3-7.
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AT32UC3C Table 3-7.
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AT32UC3C Table 3-7. Signal Description List Signal Name Function DP USB Device Port Data + Analog VBUS USB VBUS Monitor and OTG Negociation Analog Input ID ID Pin of the USB Bus Input VBOF USB VBUS On/off: bus power control port output 3.4 3.4.1 Type Active Level Comments I/O Line Considerations JTAG pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled.
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AT32UC3C 4. Processor and Architecture Rev: 2.1.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 4.1 Features • 32-bit load/store AVR32A RISC architecture – – – – – • • • • 4.
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AT32UC3C single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 4.
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AT32UC3C OCD interface Reset interface Overview of the AVR32UC CPU Interrupt controller interface Figure 4-1. OCD system Power/ Reset control AVR32UC CPU pipeline MPU 4.3.
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AT32UC3C Figure 4-2. The AVR32UC Pipeline MUL IF ID Prefetch unit Decode unit Regfile Read ALU LS 4.3.2 4.3.2.1 Multiply unit Regfile write ALU unit Load-store unit AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts.
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AT32UC3C 4.3.2.5 Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. 4.3.2.
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AT32UC3C 4.4 4.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 4-3.
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AT32UC3C Figure 4-5. The Status Register Low Halfword Bit 15 Bit 0 - T - - - - - - - - L Q V N Z C Bit name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 4.4.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Table 4-2. Overview of Execution Modes, their Priorities and Privilege Levels.
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AT32UC3C Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 4.4.4 Secure State The AVR32 can be set in a secure state, that allows a part of the code to execute in a state with higher security levels. The rest of the code can not access resources reserved for this secure code. Secure State is used to implement FlashVault technology. Refer to the AVR32UC Technical Reference Manual for details.
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AT32UC3C Table 4-3.
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AT32UC3C Table 4-3. 4.
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AT32UC3C relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including interrupt requests, yielding a uniform event handling scheme.
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AT32UC3C 4.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers.
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AT32UC3C than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4 on page 38. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floatingpoint unit.
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AT32UC3C Table 4-4.
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AT32UC3C 5. Memories 5.
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AT32UC3C 5.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32UC CPU uses unsegmented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space is mapped as follows: Table 5-1.
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AT32UC3C Table 5-2. 5.3 Flash Memory Parameters Part Number Flash Size (FLASH_PW) Number of pages (FLASH_P) Page size (FLASH_W) AT32UC3C0512C AT32UC3C1512C AT32UC3C2512C 512 Kbytes 1024 128 words AT32UC3C0256C AT32UC3C1256C AT32UC3C2256C 256 Kbytes 512 128 words AT32UC3C0128C AT32UC3C1128C AT32UC3C2128C 128 Kbytes 256 128 words AT32UC3C064C AT32UC3C164C AT32UC3C264C 64 Kbytes 128 128 words Peripheral Address Map Table 5-3.
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AT32UC3C Table 5-3. Peripheral Address Mapping 0xFFFE0000 HFLASHC Flash Controller - HFLASHC 0xFFFE1000 USBC USB 2.
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AT32UC3C Table 5-3.
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AT32UC3C The following GPIO registers are mapped on the local bus: Table 5-4.
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AT32UC3C Table 5-4.
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AT32UC3C 6. Supply and Startup Considerations 6.1 6.1.1 Supply Considerations Power Supplies The AT32UC3C has several types of power supply pins: • VDDIO pins (VDDIO1, VDDIO2, VDDIO3): Power I/O lines. Two voltage ranges are available: 5V or 3.3V nominal. The VDDIO pins should be connected together. • VDDANA: Powers the Analog part of the device (Analog I/Os, ADC, ACs, DACs). 2 voltage ranges • • • • • • • available: 5V or 3.3V nominal. VDDIN_5: Input voltage for the 1.8V and 3.3V regulators.
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AT32UC3C The 3.3V regulator is connected to the 5V source (VDDIN_5 pin) and its output feeds the USB pads. If the USB is not used, the 3.3V regulator can be disabled through the VREG33CTL field of the VREGCTRL SCIF register. Figure 6-1 on page 47 shows the power schematics to be used for 5V single supply mode. All I/O lines and analog blocks will be powered by the same power (VDDIN_5 = VDDIO1 = VDDIO2 = VDDIO3 = VDDANA). Figure 6-1. 5V Single Power Supply mode + 4.55.
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AT32UC3C Figure 6-2. 3 Single Power Supply Mode + 3.03.6V CIN2 VDDIO1 VDDIO2 VDDIO3 VDDIN_5 VDDANA GNDANA CIN1 BOD33 Analog: ADC, AC, DAC, ... BOD50 VDDIN_33 VDDCORE COUT2 CPU Peripherals Memories 3.3V Reg 1.8V Reg GNDIO1 GNDIO2 GNDIO3 SCIF, BOD, RCSYS COUT1 GNDPLL PLL BOD18 GNDCORE POR 6.1.4 6.1.4.1 Power-up Sequence Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Table 40-2 on page 1249 .
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AT32UC3C 6.2 Startup Considerations This chapter summarizes the boot sequence of the AT32UC3C. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 6.2.1 Starting of clocks At power-up, the BOD33 and the BOD18 are enabled. The device will be held in a reset state by the power-up circuitry, until the VDDIN_33 (resp. VDDCORE) has reached the reset threshold of the BOD33 (resp BOD18).
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AT32UC3C 7. Power Manager (PM) Rev: 4.1.2.4 7.1 Features • • • • • • 7.
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AT32UC3C 7.3 Block Diagram Figure 7-1. PM Block Diagram Main Clock Sources Synchronous Clock Generator Synchronous clocks CPU, HSB, PBx Interrupts Sleep Controller Sleep Instruction Reset Controller Resets Reset Sources Power-on Reset Detector(s) External Reset Pin 7.4 I/O Lines Description Table 7-1. I/O Lines Description Name Description Type Active Level RESET_N Reset Input Low 7.5 7.5.
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AT32UC3C 7.6 Functional Description 7.6.1 Synchronous Clocks The System RC Oscillator (RCSYS) and a selection of other clock sources can provide the source for the main clock, which is the origin for the synchronous CPU/HSB and PBx module clocks. For details about the other main clock sources, please refer to the Main Clock Control (MCCTRL) register description. The synchronous clocks can run of the main clock and all the 8bit prescaler settings as long as fCPU ≥ fPBx,.
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AT32UC3C Similarly, the PBx clocks can be divided by writing their respective Clock Select (PBxSEL) registers to get the divided PBx frequency: fPBx = fmain / 2(PBSEL+1) The PBx clock frequency can not exceed the CPU clock frequency. The user must select a PBxSEL.PBSEL value greater than or equal to the CPUSEL.CPUSEL value, so that fCPU ≥ fPBx. If the user selects division factors that will result in fCPU< fPBx, the Power Manager will automatically change the PBxSEL.
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AT32UC3C 7.6.3.1 Entering and exiting sleep modes The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains. The modules will be halted regardless of the bit settings in the mask registers. Clock sources can also be switched off to save power. Some of these have a relatively long start-up time, and are only switched off when very low power consumption is required. The CPU and affected modules are restarted when the sleep mode is exited.
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AT32UC3C Table 7-3. (1) Index Wake-up Sources Sleep Mode Wake-up Sources 0 Idle Synchronous, Asynchronous 1 Frozen Synchronous(2), Asynchronous 2 Standby Asynchronous 3 Stop Asynchronous 4 DeepStop Asynchronous 5 Static Asynchronous(3) Notes: 1. The sleep mode index is used as argument for the sleep instruction. 2. Only PB modules operational, as HSB module clocks are stopped. 3. WDT only available if clocked from pre-enabled OSC32K. 7.6.3.
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AT32UC3C It is also possible to reset the device by pulling the RESET_N pin low. This pin has an internal pull-up, and does not need to be driven externally during normal operation. Table 7-4 on page 56 lists these and other reset sources supported by the Reset Controller. Figure 7-3.
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AT32UC3C 7.6.5.1 Power-on Reset Detector The Power-on Reset 1.8V (POR18) detector monitors the VDDCORE supply pin and generates a Power-on Reset (POR) when the device is powered on. The POR is active until the VDDCORE voltage is above the power-on threshold level (VPOT). The POR will be re-generated if the voltage drops below the power-on threshold level. See Electrical Characteristics for parametric details. 7.6.5.2 External Reset The external reset detector monitors the RESET_N pin state.
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AT32UC3C Register (ICR). Because all the interrupt sources are ORed together, the interrupt request from the Power Manager will remain active until all the bits in ISR are cleared.
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AT32UC3C 7.7 User Interface Table 7-5.
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AT32UC3C 7.7.1 Name: Main Clock Control MCCTRL Access Type: Read/Write Offset: 0x0000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - MCSEL • MCSEL: Main Clock Select Table 7-6. Main clocks in AT32UC3C.
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AT32UC3C 7.7.2 Name: CPU Clock Select CPUSEL Access Type: Read/Write Offset: 0x0004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 CPUDIV - - - - CPUSEL • CPUDIV, CPUSEL: CPU Division and Clock Select • CPUDIV = 0: CPU clock equals main clock. • CPUDIV = 1: CPU clock equals main clock divided by 2(CPUSEL+1).
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AT32UC3C 7.7.
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AT32UC3C 7.7.4 Name: PBx Clock Select PBxSEL Access Type: Read/Write Offset: 0x000C, 0x0010, 0x0014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PBDIV - - - - PBSEL • PBDIV, PBSEL: PBx Division and Clock Select • PBDIV = 0: PBx clock equals main clock. • PBDIV = 1: PBx clock equals main clock divided by 2(PBSEL+1).
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AT32UC3C 7.7.5 Name: Clock Mask CPU/HSB/PBA/PBBMASK Access Type: Read/Write Offset: 0x0020, 0x0024, 0x0028, 0x002C, 0x0030 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MASK[31:24] 23 22 21 20 MASK[23:16] 15 14 13 12 MASK[15:8] 7 6 5 4 MASK[7:0] • MASK: Clock Mask • If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode.
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AT32UC3C Table 7-7. Maskable module clocks in AT32UC3C. Bit CPUMASK HSBMASK PBAMASK PBBMASK PBCMASK 13 - - TWIM1 - - 14 - - TWIS0 - - 15 - - TWIS1 - - 16 - - IISC - - 17 - - PWM - - 18 - - QDEC0 - - 19 - - QDEC1 - - 20 - - TC1 - - 21 - - - - - 22 - - ACIFA0 - - 23 - - ACIFA1 - - 24 - - DACIFB0 - - 25 - - DACIFB1 - - 26 - - AW - - 31:27 - - - - - Note that this register is protected by a lock.
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AT32UC3C 7.7.6 Name: Divided Clock Mask PBADIVMASK/PBBDIVMASK/PBCDIVMASK Access Type: Read/Write Offset: 0x0040, 0x0044, 0x0048 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - MASK[6:0] • MASK: Clock Mask If bit n is written to zero, the clock divided by 2(n+1) is stopped.
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AT32UC3C Table 7-9. Bit PBC Divided Clock Mask USART1 USART4 TC0 4 - TIMER0_CLOCK4 5 - - 6 - TIMER0_CLOCK5 Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details.
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AT32UC3C 7.7.7 Name: Clock Failure Detector Control Register CFDCTRL Access Type: Read/Write Offset: 0x0054 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - CFDEN • SFV: Store Final Value • 0: The register is read/write • 1: The register is read-only, to protect against further accidental writes.
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AT32UC3C 7.7.8 Name: PM Unlock Register UNLOCK Access Type: Write-Only Offset: 0x0058 Reset Value: - 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 ADDR[9:8] 1 0 ADDR[7:0] To unlock a write protected register, first write to the UNLOCK register with the address of the register to unlock in the ADDR field and 0xAA in the KEY field.
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AT32UC3C 7.7.9 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x0C0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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AT32UC3C 7.7.10 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x0C4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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AT32UC3C 7.7.11 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x0C8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one.
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AT32UC3C 7.7.12 Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x0CC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one.
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AT32UC3C 7.7.13 Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x0D0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR.
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AT32UC3C 7.7.14 Status Register Name: SR Access Type: Read-only Offset: 0x0D4 Reset Value: 0x00000020 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD • AE: Access Error 0: No access error has occured. 1: A write to lock protected register without unlocking it has occured.
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AT32UC3C 7.7.15 Name: Reset Cause RCAUSE Access Type: Read-only Offset: 0x0180 Reset Value: Latest Reset Source 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - BOD33 - AWIRE - - OCDRST 7 6 5 4 3 2 1 0 - JTAG WDT EXT BOD POR CPUERR • BOD33: Brown-out 3.3V reset The CPU was reset due to the supply voltage being lower than the 3.3V Supply Monitor (BOD33) threshold level.
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AT32UC3C 7.7.16 Wake Cause Register Register name WCAUSE Register access Read-only Offset: 0x0184 Reset Value: Latest Reset Source 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 2 1 0 WCAUSE[17:16] WCAUSE[15:8] 7 6 5 4 3 WCAUSE[7:0] • A bit in this register is set on wake up caused by the peripheral referred to in Table 7-10. Table 7-10.
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AT32UC3C 7.7.17 Asynchronous Wake Up Enable Register Register name AWEN Register access Read/Write Offset: 0x0188 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 AWEN[31:24] 23 22 21 20 AWEN[23:16] 15 14 13 12 AWEN[15:8] 7 6 5 4 AWEN[7:0] Each bit in this register corresponds to an asynchronous wake up, according to Table 7-11. 0: The corresponding wake up is disabled. 1: The corresponding wake up is enabled Table 7-11.
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AT32UC3C 7.7.18 Name: Configuration Register CONFIG Access Type: Read-Only Offset: 0x03F8 Reset Value: 0x000000C3 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - PBD PBC PBB PBA HSBPEVC This register shows the configuration of the PM. • HSBPEVC:HSB PEVC Clock Implemented • • • • 0: HSBPEVC not implemented. 1: HSBPEVC implemented.
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AT32UC3C 7.7.19 Name: Version Register VERSION Access Type: Read-Only Offset: 0x03FC Reset Value: 0x00000410 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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AT32UC3C 7.8 Module Configuration The specific configuration for each PM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 7-12. Module name Clock name Description PM CLK_PM Peripheral Bus clock from the PBA clock domain Table 7-13. Table 7-14.
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AT32UC3C 8. System Control Interface (SCIF) Rev: 1.0.2.0 8.1 Features • • • • • • • • • • • • 8.2 Controls integrated oscillators and PLLs Supports 2x General Purpose crystal oscillators, 0.
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AT32UC3C 8.4.2 Interrupt The SCIF interrupt line is connected to one of the internal sources of the interrupt controller. Using the SCIF interrupt requires the interrupt controller to be programmed first. 8.4.3 Debug Operation The SCIF module does not interact with debug operations. 8.4.4 Clocks The SCIF controls all oscillators on the part.
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AT32UC3C Figure 8-1. Oscillator connections UC3C C LEXT XOUT Ci CL XIN 8.5.2 C LEXT 32KHz Oscillator (OSC32K) Operation The 32 KHz oscillator (OSC32K) operates as described for the Oscillator above. The 32 KHz oscillator is used as source clock for the Asynchronous Timer and the Watchdog Timer. The 32KHz oscillator can be used as source for the generic clocks, as described in ”Generic Clocks” on page 85.
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AT32UC3C logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from receiving a too high frequency and thus becoming unstable. Figure 8-2. PLL with control logic and filters PLLMUL Output Divider Osc0 clock 0 Osc1 clock 1 Input Divider PLLOSC 8.5.3.1 PLLDIV fIN PLL Mask PLL clock LOCK PLLEN PLLOPT Enabling the PLL PLLn is enabled by writing a one to the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1 as clock source.
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AT32UC3C Figure 8-3. Generic clock generation Sleep Controller 0 Mask Divider OSCSEL 8.5.4.1 DIV Generic Clock 1 DIVEN CEN Enabling a generic clock A generic clock is enabled by writing a one to the CEN bit in GCCTRL to one. Each generic clock can individually select a clock source by setting the OSCSEL bits. The source clock can optionally be divided by writing a one to DIVEN and the division factor to DIV, resulting in the output frequency: fGCLK = fSRC / (2*(DIV+1)) 8.5.4.
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AT32UC3C Table 8-2. Generic clock allocation Clock number 8.5.5 Function Name 3 - 4 PWM GCLK_PWM 5 QDEC0 GCLK_QDEC0 6 QDEC1 GCLK_QDEC1 7 GCLK event, mapped to event number 16. See the Module Configuration of PEVC for more details. 8 GCLK event, mapped to event number 17. See the Module Configuration of PEVC for more details. 9 GCLK[0] output pin 10 GCLK[1] output pin 11 IISC GCLK_IISC 1.8V Brown Out Detection (BOD18) The 1.
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AT32UC3C If the JTAG or the AWIRE is enabled, the BOD33 reset and interrupt will be masked. See Electrical Characteristics for parametric details. To prevent unexpected writes due to software bugs, write access to this register is protected by a locking mechanism, for details please refer to the UNLOCK register description. 8.5.7 5V Brown Out Detection (BOD50) The 5V Brown-Out Detector (BOD50) monitors the VDDIN_5 supply pin and compares the supply voltage to the brown-out detection level, as set in BOD50.
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AT32UC3C 8.5.10 System RC Oscillator (RCSYS) The system RC oscillator (RCSYS) has a 3 cycles startup time, and is always available except in the STATIC sleep mode. The system RC oscillator operates at a nominal frequency of 115 kHz, and is calibrated using the RCCR.CALIB Calibration field. After a Power On Reset, the RCCR.CALIB field is loaded with a factory defined value stored in the Flash fuses.
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AT32UC3C • BOD50DET - 5V Brown out detection: – Set when a 0 to 1 transition on the PCLKSR.BOD50DET bit is detected. • BOD33DET - 3.3V Brown out detection: – Set when a 0 to 1 transition on the PCLKSR.BOD33DET bit is detected. • BODDET - 1.8V Brown out detection: – Set when a 0 to 1 transition on the PCLKSR.BODDET bit is detected. • PLL1LOCK - PLL1 locked: – Set when a 0 to 1 transition on the PCLKSR.PLL1LOCK bit is detected. • PLL0LOCK - PLL0 locked: – Set when an 0 to 1 transition on the PCLKSR.
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AT32UC3C 8.6 User Interface Table 8-3.
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AT32UC3C Table 8-3. SCIF Register Memory Map Offset Register Register Name Access Reset 0x03F4 GPLP Version Register GPLPVERSION Read-Only -(1) 0x03F8 Generic Clock Version Register GCLKVERSION Read-Only -(1) 0x03FC SCIF Version Register VERSION Read-Only -(1) Note: 1. The reset value is device specific. Please refer to the Module Configuration section at the end of this chapter.
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AT32UC3C 8.6.1 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x0000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - PLL1_LOCK LOST PLL0_LOCK LOST BOD50DET 7 6 5 4 3 2 1 0 BOD33DET BODDET PLL1_LOCK PLL0_LOCK RCOSC8MRDY OSC32RDY OSC1RDY OSC0RDY Writing a zero to a bit in this register has no effect.
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AT32UC3C 8.6.2 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x0004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - PLL1_LOCK LOST PLL0_LOCK LOST BOD50DET 7 6 5 4 3 2 1 0 BOD33DET BODDET PLL1_LOCK PLL0_LOCK RCOSC8MR DY OSC32RDY OSC1RDY OSC0RDY Writing a zero to a bit in this register has no effect.
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AT32UC3C 8.6.3 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x0008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - PLL1_LOCK LOST PLL0_LOCK LOST BOD50DET 7 6 5 4 3 2 1 0 BOD33DET BODDET PLL1_LOCK PLL0_LOCK RCOSC8MR DY OSC32RDY OSC1RDY OSC0RDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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AT32UC3C 8.6.4 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x000C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - PLL1_LOCK LOST PLL0_LOCK LOST BOD50DET 7 6 5 4 3 2 1 0 BOD33DET BODDET PLL1_LOCK PLL0_LOCK RCOSC8MR DY OSC32RDY OSC1RDY OSC0RDY 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending.
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AT32UC3C 8.6.5 Name: Interrupt Clear Register ICR Access Type: Write-only Offset: 0x0010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - PLL1_LOCK LOST PLL0_LOCK LOST BOD50DET 7 6 5 4 3 2 1 0 BOD33DET BODDET PLL1_LOCK PLL0_LOCK RCOSC8MR DY OSC32RDY OSC1RDY OSC0RDY Writing a zero to a bit in this register has no effect.
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AT32UC3C 8.6.6 Name: Power and Clocks Status Register PCLKSR Access Type: Read-Only Offset: 0x0014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - PLL1_LOCK LOST PLL0_LOCK LOST BOD50DET 7 6 5 4 3 2 1 0 BOD33DET BODDET PLL1_LOCK PLL0_LOCK RCOSC8MR DY OSC32RDY OSC1RDY OSC0RDY • AE: SCIF Access Error 0: No access error has occurred on the SCIF.
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AT32UC3C • RCOSC8MRDY: 8MHz / 1MHz RCOSC Ready 0: 8MHz / 1MHz RC Oscillator not enabled or not ready. 1: 8MHz / 1MHz RC Oscillator is stable and ready to be used as clock source. • OSC32RDY: 32 KHz oscillator Ready 0: Oscillator 32 not enabled or not ready. 1: Oscillator 32 is stable and ready to be used as clock source. • OSC1RDY: OSC1Ready 0: Oscillator not enabled or not ready. 1: Oscillator is stable and ready to be used as clock source. • OSC0RDY: OSC0Ready 0: Oscillator not enabled or not ready.
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AT32UC3C 8.6.7 Name: Unlock Register UNLOCK Access Type: Write-Only Offset: 0x0018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 ADDR[9:8] 1 0 ADDR[7:0] To unlock a write protected register, first write to the UNLOCK register with the address of the register to unlock in the ADDR field and 0xAA in the KEY field.
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AT32UC3C 8.6.8 Name: PLL Control Register PLL0,1 Access Type: Read/Write Offset: 0x001C,0x0020 Reset Value: 0x00000000 31 30 29 28 - - 23 22 21 20 - - - - 15 14 13 12 - - - - 7 6 5 4 - - 27 26 25 24 18 17 16 9 8 1 0 PLLCOUNT PLLOPT 19 PLLMUL 11 10 PLLDIV 3 2 PLLOSC PLLEN • PLLCOUNT: PLL Count Specifies the number of slow clock cycles before ISR.
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AT32UC3C Table 8-4. PLLOPT Fields Description Description PLLOPT[0]: VCO frequency 0 80MHz
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AT32UC3C 8.6.9 Name: Oscillator Control Register OSCCTRL0,1 Access Type: Read/Write Offset: 0x0024,0x0028 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - OSCEN 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 3 1 0 - - - - AGC STARTUP 2 GAIN MODE • OSCEN 0: Disable the Oscillator. 1: Enable the Oscillator. • STARTUP: Oscillator Startup Time Select startup time for the oscillator. Table 8-5.
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AT32UC3C Table 8-5. Startup time for oscillators 0 and 1 STARTUP Number of RC oscillator clock cycle Approximative Equivalent time (RCSYS = 115 kHz) 13 512 4.5 ms 14 1024 9 ms 15 Reserved Reserved • AGC: Automatic Gain Control 0: Disable the automatic gain control of the Oscillator. 1: Enable the automatic gain control of the Oscillator. • GAIN: Oscillator Gain Set the gain of the Oscillator. Table 8-6.
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AT32UC3C 8.6.10 Name: 1.8V BOD Control Register BOD Access Type: Read/Write Offset: 0x002C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 - HYST CTRL 1 0 LEVEL • SFV: Store Final Value 0: The register is read/write. 1: The register is read-only, to protect against further accidental writes.
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AT32UC3C • LEVEL: BOD18 Level This field sets the triggering threshold of the BOD18. See Electrical Characteristics for actual voltage levels. Note that any change to the LEVEL field of the BOD register should be done with the BOD18 deactivated to avoid spurious reset or interrupt. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details.
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AT32UC3C 8.6.11 Name: Bandgap Calibration Register BGCR Access Type: Read/Write Offset: 0x0030 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 - - - - - 0 CALIB • SFV: Store Final Value 0: The register is read/write. 1: The register is read-only, to protect against further accidental writes.
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AT32UC3C 8.6.12 Name: 3.3V BOD Control Register BOD33 Access Type: Read/Write Offset: 0x0034 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 - HYST CTRL 1 0 LEVEL • SFV: Store Final Value 0: The register is read/write. 1: The register is read-only, to protect against further accidental writes.
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AT32UC3C • LEVEL: BOD33 Level This field sets the triggering threshold of the BOD33. See Electrical Characteristics for actual voltage levels. Note that any change to the LEVEL field of the BOD33 register should be done with the BOD33 deactivated to avoid spurious reset or interrupt. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details.
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AT32UC3C 8.6.13 Name: 5V BOD Control Register BOD50 Access Type: Read/Write Offset: 0x0038 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - CTRL 7 6 5 4 3 2 1 0 - HYST LEVEL • SFV: Store Final Value 0: The register is read/write. 1: The register is read-only, to protect against further accidental writes. • CTRL: BOD50 Control 0: BOD50 is off.
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AT32UC3C 8.6.14 Name: Voltage Regulator Calibration Register VREGCR Access Type: Read/Write Offset: 0x003C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - CALIB • SFV: Store Final Value 0: The register is read/write. 1: The register is read-only, to protect against further accidental writes.
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AT32UC3C 8.6.15 Name: Voltage Regulator Control Register VREGCTRL Access Type: Read/Write Offset: 0x0040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - VREG33CTL - • SFV: Store Final Value 0: The register is read/write. 1: The register is read-only, to protect against further accidental writes. • VREG33CTL: 3.
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AT32UC3C 8.6.16 Name: RCSYS Calibration Register RCCR Access Type: Read/Write Offset: 0x0044 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 CALIB[9:8] 1 0 CALIB[7:0] • FCD: Flash Calibration Done Set to 1 when CALIB field has been updated by the Flash fuses after a reset. 0: The flash calibration will be redone after any reset.
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AT32UC3C 8.6.17 Name: 8MHz / 1MHz RC Oscillator Control Register RCCR8 Access Type: Read/Write Offset: 0x0048 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - FREQMODE RCOSC8_EN 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 CALIB[7:0] • FREQMODE: Frequency Mode 0: the RC8M RC oscillator will run at 8 MHz. 1: the RC8M RC oscillator will run at 1 MHz.
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AT32UC3C 8.6.18 Name: 32KHz Oscillator Control Register OSCCTRL32 Access Type: Read/Write Offset: 0x004C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - 15 14 13 12 11 10 - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - OSC32EN STARTUP 9 8 MODE Note: This register is only reset by Power-On Reset. • STARTUP: Oscillator Startup Time Select startup time for 32 KHz oscillator. Table 8-10.
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AT32UC3C • MODE: Oscillator Mode Table 8-11. MODE Operation mode for 32 KHz oscillator Description 0 External clock connected to XIN32, XOUT32 can be used as I/O (no crystal) 1 2-pin crystal mode. Crystal is connected to XIN32/XOUT32 2 2-pin crystal and I-Current mode. Crystal is connected to XIN32/XOUT32 3 Reserved • OSC32EN: Enable the 32 KHz oscillator 0: 32 KHz Oscillator is disabled. 1: 32 KHz Oscillator is enabled. Note that this register is protected by a lock.
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AT32UC3C 8.6.19 Name: 120MHz RC Oscillator Control Register RC120MCR Access Type: Read/Write Offset: 0x0058 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - EN • EN: RC120M Enable 0: Clock is stopped. 1: Clock is running. Note that this register is protected by a lock.
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AT32UC3C 8.6.20 Name: General Purpose Low-power Register 0/1 GPLP0,1 Access Type: Read/Write Offset: 0x005C,0x0060 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset will keep the bits of these registers untouched.
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AT32UC3C 8.6.21 Name: Generic Clock Control GCCTRL Access Type: Read/Write Offset: 0x0064-0x008C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 DIV 15 14 13 12 OSCSEL 7 6 5 4 3 2 1 0 - - - - - - DIVEN CEN There is one GCCTRL register per generic clock in the device. • DIV: Division Factor • OSCSEL: Oscillator Select Table 8-12.
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AT32UC3C • DIVEN: Divide Enable 0: The generic clock equals the undivided source clock. 1: The generic clock equals the source clock divided by 2*(DIV+1). • CEN: Clock Enable 0: Clock is stopped. 1: Clock is running.
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AT32UC3C 8.6.22 Name: PLL Interface Version Register PLLVERSION Access Type: Read-Only Offset: 0x03C8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 8.6.23 Name: Oscillator Interface Version Register OSCVERSION Access Type: Read-Only Offset: 0x03CC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 8.6.24 Name: 1.8V BOD Interface Version Register BODVERSION Access Type: Read-Only Offset: 0x03D0 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 8.6.25 Name: 3.3V / 5V BOD Interface Version Register BODBVERSION Access Type: Read-Only Offset: 0x03D4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 8.6.26 Name: Voltage Regulator Interface Version Register VREGVERSION Access Type: Read-Only Offset: 0x03D8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 8.6.27 Name: RCSYS Interface Version Register RCCRVERSION Access Type: Read-Only Offset: 0x03DC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 8.6.28 Name: 8MHz / 1MHz RCOSC Interface Version Register RCCR8VERSION Access Type: Read-Only Offset: 0x03E0 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 8.6.29 Name: 32KHz Oscillator Interface Version Register OSC32VERSION Access Type: Read-Only Offset: 0x03E4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 8.6.30 Name: 120MHz RC Oscillator Version Register RC120MVERSION Access Type: Read-Only Offset: 0x03F0 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 8.6.31 Name: GPLP Version Register GPLPVERSION Access Type: Read-Only Offset: 0x03F4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 8.6.32 Name: Generic Clock Version Register GCLKVERSION Access Type: Read-Only Offset: 0x03F8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 8.6.33 Name: SCIF Version Register VERSION Access Type: Read-Only Offset: 0x03FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:0] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 8.7 Module Configuration The specific configuration for each SCIF instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 8-13. SCIF Clock Name Module name Clock Name Description SCIF CLK_SCIF Peripheral Bus clock from the PBA clock domain Table 8-14.
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AT32UC3C 9. Asynchronous Timer (AST) Rev: 2.0.0.1 9.1 Features • 32-bit counter with 32-bit prescaler • Clocked Source • • • • 9.
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AT32UC3C 9.3 Block Diagram Figure 9-1. Asynchronous Timer block diagram WAKE ENABLE REGISTER CLK_AST CLK_AST CONTROL REGISTER CLK_AST CSSEL EN Wake Control COUNTER VALUE Wake PSEL 32 KHz RC OSC CLK_AST_PRSC PB clock 32-bit Prescaler CLK_AST_CNT 32-bit counter OVF GCLK IRQs DIGITAL TUNER REGISTER 9.
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AT32UC3C • Peripheral Bus clock (PB clock). This is the clock of the peripheral bus the AST is connected to. • Generic clock (GCLK). One of the generic clocks is connected to the AST. This clock must be enabled before use, and remains enabled in sleep modes when the PB clock is active. 9.4.3 Interrupt The AST interrupt request lines are connected to the interrupt controller. Using the AST interrupts requires the interrupt controller to be programmed first. 9.4.
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AT32UC3C 9.5.1.2 Changing the source clock The CLK_AST_PRSC must be disabled before switching to another source clock. The Clock Busy bit in the Status Register (SR.CLKBUSY) indicates whether the clock is busy or not. This bit is set when the CEN bit in the CLOCK register is changed, and cleared when the CLOCK register can be changed. To change the clock: • Write a zero to CLOCK.CEN to disable the clock, without changing CLOCK.CSSEL • Wait until SR.CLKBUSY reads as zero • Write the selected value to CLOCK.
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AT32UC3C 9.5.2.3 Calendar operation When the CAL bit in the Control Register is one, the counter operates in calendar mode. Before this mode is enabled, the prescaler should be set up to give a pulse every second. The date and time can then be read from or written to the Calendar Value (CALV) register. Time is reported as seconds, minutes, and hours according to the 24-hour clock format. Date is the numeral date of month (starting on 1).
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AT32UC3C prescaler when the AST is enabled. The bit is selected by the Interval Select field in the corresponding Periodic Interval Register (PIRn.INSEL), resulting in a periodic interrupt frequency of f CS f PA = -----------------------INSEL + 1 2 where fCS is the frequency of the selected clock source. The corresponding PERn bit in the Status Register (SR) will be set when the selected bit in the prescaler has a 0-to-1 transition.
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AT32UC3C The peripheral event will be generated if the corresponding bit in the Event Mask (EVM) register is set. Bits in EVM register are set by writing a one to the corresponding bit in the Event Enable (EVE) register, and cleared by writing a one to the corresponding bit in the Event Disable (EVD) register. 9.5.5 AST wakeup The AST can wake up the CPU directly, without the need to trigger an interrupt.
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AT32UC3C 9.5.7 Synchronization As the prescaler and counter operate asynchronously from the user interface, the AST needs a few clock cycles to synchronize values written to the CR, CV, SCR, WER, EVE, EVD, PIRx, ARx and DTR registers. The Busy bit in the Status Register (SR.BUSY) indicates that the synchronization is ongoing. During this time, writes to these registers will be discarded. Note that synchronization takes place also if the prescaler is clocked from CLK_AST.
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AT32UC3C 9.6 User Interface Table 9-1.
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AT32UC3C 9.6.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 12 11 10 9 8 - - - - - - CA1 CA0 7 6 5 4 3 2 1 0 - - - - CAL PCLR EN PSEL When the SR.BUSY bit is set, writes to this register will be discarded and this register will read as zero.
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AT32UC3C 9.6.2 Name: Counter Value CV Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VALUE[31:24] 23 22 21 20 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] When the SR.BUSY bit is set, writes to this register will be discarded and this register will read as zero. • VALUE: AST Value • The current value of the AST counter.
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AT32UC3C 9.6.3 Name: Status Register SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKREADY CLKBUSY - - READY BUSY 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF • CLKREADY: Clock ready • • • • • • This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the SR.
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AT32UC3C 9.6.4 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKREADY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set, writes to this register will be discarded. Writing a zero to a bit in this register has no effect.
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AT32UC3C 9.6.5 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKREADY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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AT32UC3C 9.6.6 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKREADY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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AT32UC3C 9.6.7 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKREADY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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AT32UC3C 9.6.8 Name: Wake Enable Register WER Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. This register enables the wakeup signal from the AST.
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AT32UC3C 9.6.9 Name: Alarm Register AR0/1 Access Type: Read/Write Offset: 0x20/0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VALUE[31:24] 23 22 21 20 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • VALUE: Alarm Value • When the counter reaches this value, an alarm is generated.
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AT32UC3C 9.6.10 Name: Periodic Interval Register PIR0/1 Access Type: Read/Write Offset: 0x30/0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - INSEL When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero.
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AT32UC3C 9.6.11 Name: Clock Control Register CLOCK Access Type: Read/Write Offset: 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - 7 6 5 4 3 2 1 0 - - - - - - - CEN CSSEL When writing to this register, follow the sequence in Section 9.5.1.
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AT32UC3C 9.6.12 Name: Digital Tuner Register DTR Access Type: Read/Write Offset: 0x44 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 VALUE 7 6 5 - - ADD 4 EXP When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • VALUE: 0: The frequency is unchanged.
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AT32UC3C 9.6.13 Name: Event Enable Register EVE Access Type: Write-only Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. Writing a zero to a bit in this register has no effect.
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AT32UC3C 9.6.14 Name: Event Disable Register EVD Access Type: Write-only Offset: 0x4C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. Writing a zero to a bit in this register has no effect.
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AT32UC3C 9.6.15 Name: Event Mask Register EVM Access Type: Read-only Offset: 0x50 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF 0: The corresponding peripheral event is disabled. 1: The corresponding peripheral event is enabled.
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AT32UC3C 9.6.16 Name: Calendar Value CALV Access Type: Read/Write Offset: 0x54 Reset Value: 0x00000000 31 30 29 28 27 26 25 YEAR 23 22 21 MONTH[3:2] 20 MONTH[1:0] 15 19 18 17 DAY 14 13 12 6 16 HOUR[4] 11 10 HOUR[3:0] 7 24 9 8 1 0 MIN[5:2] 5 4 3 MIN[1:0] 2 SEC When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • YEAR: Year • • • • • • Current year. The year is considered a leap year if YEAR[1:0] = 0.
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AT32UC3C 9.6.17 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0xF0 Reset Value: - 31 30 29 - - - 23 22 21 - - - 15 14 13 12 PIR1WA PIR0WA - NUMPIR 7 6 5 4 - • • • • • • • 28 27 26 25 24 17 16 9 8 PER1VALUE 20 19 18 PER0VALUE DTEXPVALUE 11 10 NUMAR 3 2 1 0 DTEXPWA DT This register gives the configuration used in the specific device. Also refer to the Module Configuration section.
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AT32UC3C 9.6.18 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: 0x00000300 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant number • Reserved. No functionality associated. • VERSION: Version number • Version of the module. No functionality associated.
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AT32UC3C 9.7 Module configuration The specific configuration for each AST instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 9-3. Module configuration Feature AST Number of timer alarms 2 Number of periodic alarms 2 Digital tuner On Table 9-4. Module name AST Table 9-5.
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AT32UC3C 10. Watchdog Timer (WDT) Rev: 4.1.0.0 10.1 Features • • • • • 10.2 Watchdog Timer counter with 32-bit counter Timing window watchdog Clocked from system RC oscillator or the 32 KHz crystal oscillator Configuration lock WDT may be enabled at reset by a fuse Overview The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the software. This allows the device to recover from a condition that has caused the system to be unstable.
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AT32UC3C 10.4.1 Power Management When the WDT is enabled, the WDT remains clocked in all sleep modes. It is not possible to enter sleep modes where the source clock of CLK_CNT is stopped. Attempting to do so will result in the device entering the lowest sleep mode where the source clock is running, leaving the WDT operational. Please refer to the Power Manager chapter for details about sleep modes. After a watchdog reset the WDT bit in the Reset Cause Register (RCAUSE) in the Power Manager will be set.
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AT32UC3C To change the clock for the WDT the following steps need to be taken. Note that the WDT should always be disabled before changing the CLK_CNT source: 1. Write a zero to the Clock Enable (CEN) bit in the CTRL Register, leaving the other bits as they are in the CTRL Register. This will stop CLK_CNT. 2. Read back the CTRL Register until the CEN bit reads zero. The clock has now been stopped. 3.
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AT32UC3C Figure 10-2. Basic Mode WDT Timing Diagram, normal operation. t= t 0 T psel T im e o u t W rite o n e to C L R .W D T C L R W a tc h d o g re s e t If the WDT counter is not cleared within Tpsel a watchdog reset will be issued at the end of Tpsel, see Figure 10-3 on page 165. Figure 10-3. Basic Mode WDT Timing Diagram, no clear within Tpsel. t= t 0 T p se l T im eo u t W rite o n e to C LR .W D T C LR W a tch d og re set 10.5.1.
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AT32UC3C The PSEL and Time Ban Prescale Select (TBAN) fields in the CTRL Register selects the WDT timeout period Ttimeout = Ttban + Tpsel = (2(TBAN+1) + 2(PSEL+1)) / fclk_cnt where Ttban sets the time period when clearing the WDT counter by writing to the CLR.WDTCLR bit is not allowed. Doing so will result in a watchdog reset, the device will receive a reset and the code will start executing form the boot vector, see Figure 10-5 on page 166. The WDT counter will be cleared. Writing a one to the CLR.
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AT32UC3C 10.5.3 Disabling the WDT The WDT is disabled by writing a zero to the CTRL.EN bit. When disabling the WDT no other bits in the CTRL Register should be changed until the CTRL.EN bit reads back as zero. If the CTRL.CEN bit is written to zero, the CTRL.EN bit will never read back as zero if changing the value from one to zero. 10.5.4 Flash Calibration The WDT can be enabled at reset. This is controlled by the WDTAUTO fuse.
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AT32UC3C 10.6 User Interface Table 10-1. Note: WDT Register Memory Map Offset Register Register Name Access Reset 0x000 Control Register CTRL Read/Write 0x00010080 0x004 Clear Register CLR Write-only 0x00000000 0x008 Status Register SR Read-only 0x00000003 0x3FC Version Register VERSION Read-only -(1) 1. The reset value for this register is device specific. Please refer to the Module Configuration section at the end of this chapter.
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AT32UC3C 10.6.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x000 Reset Value: 0x00010080 31 30 29 28 27 26 25 24 19 18 17 16 CSSEL CEN 9 8 KEY 23 22 21 - 20 TBAN 15 14 13 12 11 10 - - - 7 6 5 4 3 2 1 0 FCD - - - SFV MODE DAR EN PSEL • KEY • • • • • • • This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This field always reads as zero.
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AT32UC3C • DAR: WDT Disable After Reset 0: After a watchdog reset, the WDT will still be enabled. 1: After a watchdog reset, the WDT will be disabled. • EN: WDT Enable 0: WDT is disabled. 1: WDT is enabled. After writing to this bit the read back value will not change until the WDT is enabled/disabled. This due to internal synchronization.
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AT32UC3C 10.6.2 Name: Clear Register CLR Access Type: Write-only Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - WDTCLR When the Watchdog Timer is enabled, this Register must be periodically written within the window time frame or within the watchdog timeout period, to prevent a watchdog reset.
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AT32UC3C 10.6.3 Name: Status Register SR Access Type: Read-only Offset: 0x008 Reset Value: 0x00000003 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - CLEARED WINDOW • CLEARED: WDT Counter Cleared This bit is cleared when writing a one to the CLR.WDTCLR bit. This bit is set when clearing the WDT counter is done.
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AT32UC3C 10.6.4 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 10.7 Module Configuration The specific configuration for each WDT instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 10-2. Module clock name Module name Clock name Description WDT CLK_WDT Peripheral Bus clock from the PBA clock domain Table 10-3.
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AT32UC3C 11. Interrupt Controller (INTC) Rev: 1.0.2.5 11.1 Features • Autovectored low latency interrupt service with programmable priority – 4 priority levels for regular, maskable interrupts – One Non-Maskable Interrupt • Up to 64 groups of interrupts with up to 32 interrupt requests in each group 11.2 Overview The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an interrupt request and an autovector to the CPU.
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AT32UC3C Figure 11-1. INTC Block Diagram Interrupt Controller CPU NMIREQ Masks OR IRRn GrpReqN IREQ63 IREQ34 IREQ33 IREQ32 OR GrpReq1 INT_level, offset IPRn . . . Request Masking ValReq1 INT_level, offset IPR1 . . . INTLEVEL Prioritizer . . . ValReqN SREG Masks I[3-0]M GM AUTOVECTOR IRR1 IREQ31 IREQ2 IREQ1 IREQ0 OR GrpReq0 ValReq0 IPR0 INT_level, offset IRR0 IRR Registers 11.
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AT32UC3C Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, gets its corresponding ValReq line asserted. Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status register, namely Interrupt Level 3 Mask (I3M) to Interrupt Level 0 Mask (I0M), and Global Interrupt Mask (GM).
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AT32UC3C pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared.
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AT32UC3C 11.6 User Interface Table 11-1. INTC Register Memory Map Offset Register Register Name Access Reset 0x000 Interrupt Priority Register 0 IPR0 Read/Write 0x00000000 0x004 Interrupt Priority Register 1 IPR1 Read/Write 0x00000000 ... ... ... ... ... 0x0FC Interrupt Priority Register 63 IPR63 Read/Write 0x00000000 0x100 Interrupt Request Register 0 IRR0 Read-only N/A 0x104 Interrupt Request Register 1 IRR1 Read-only N/A ... ... ... ... ...
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AT32UC3C 11.6.1 Name: Interrupt Priority Registers IPR0...
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AT32UC3C 11.6.2 Name: Interrupt Request Registers IRR0...
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AT32UC3C 11.6.3 Name: Interrupt Cause Registers ICR0...ICR3 Access Type: Read-only Offset: 0x200 - 0x20C Reset Value: N/A 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CAUSE • CAUSE: Interrupt Group Causing Interrupt of Priority n ICRn identifies the group with the highest priority that has a pending interrupt of level n.
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AT32UC3C 11.7 Interrupt Request Signal Map The various modules may output Interrupt request signals. These signals are routed to the Interrupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64 groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level.
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AT32UC3C Table 11-2.
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AT32UC3C Table 11-2.
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AT32UC3C Table 11-2.
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AT32UC3C Table 11-2.
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AT32UC3C 12. External Interrupt Controller (EIC) Rev: 3.0.2.0 12.1 Features • • • • • • • 12.2 Dedicated interrupt request for each interrupt Individually maskable interrupts Interrupt on rising or falling edge Interrupt on high or low level Asynchronous interrupts for sleep modes without clock Filtering of interrupt lines Non-Maskable NMI interrupt Overview The External Interrupt Controller (EIC) allows pins to be configured as external interrupts.
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AT32UC3C 12.4 I/O Lines Description Table 12-1. 12.5 I/O Lines Description Pin Name Pin Description Type NMI Non-Maskable Interrupt Input EXTINTn External Interrupt Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 12.5.1 I/O Lines The external interrupt pins (EXTINTn and NMI) may be multiplexed with I/O Controller lines.
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AT32UC3C Each external interrupt INTn can be configured to produce an interrupt on rising or falling edge, or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL registers. Each interrupt has a bit INTn in each of these registers. Writing a zero to the INTn bit in the MODE register enables edge triggered interrupts, while writing a one to the bit enables level triggered interrupts.
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AT32UC3C Figure 12-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on Figure 12-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on 12.6.3 Non-Maskable Interrupt The NMI supports the same features as the external interrupts, and is accessed through the same registers. The description in Section 12.6.
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AT32UC3C When CLK_SYNC is stopped only asynchronous interrupts remain active, and any short spike on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be updated on the first rising edge of CLK_SYNC. Figure 12-4. Timing Diagram, Asynchronous Interrupts C LK _SYN C C LK _SYN C E X T IN T n /N M I 12.6.5 E X T IN T n /N M I IS R .IN T n : r is in g E D G E o r h ig h LEVEL IS R .
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AT32UC3C 12.7 User Interface Table 12-2.
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AT32UC3C 12.7.
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AT32UC3C 12.7.
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AT32UC3C 12.7.
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AT32UC3C 12.7.
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AT32UC3C 12.7.
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AT32UC3C 12.7.6 Name: Mode Register MODE Access Type: Read/Write Offset: 0x014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - INT30 INT29 INT28 INT27 INT26 INT25 INT24 23 22 21 20 19 18 17 16 INT23 INT22 INT21 INT20 INT19 INT18 INT17 INT16 15 14 13 12 11 10 9 8 INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 NMI • INTn: External Interrupt n 0: The external interrupt is edge triggered.
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AT32UC3C 12.7.
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AT32UC3C 12.7.
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AT32UC3C 12.7.
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AT32UC3C 12.7.
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AT32UC3C 12.7.
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AT32UC3C 12.7.12 Enable Register Name: EN Access Type: Write-only Offset: 0x030 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - INT30 INT29 INT28 INT27 INT26 INT25 INT24 23 22 21 20 19 18 17 16 INT23 INT22 INT21 INT20 INT19 INT18 INT17 INT16 15 14 13 12 11 10 9 8 INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 NMI • INTn: External Interrupt n Writing a zero to this bit has no effect.
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AT32UC3C 12.7.
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AT32UC3C 12.7.
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AT32UC3C 12.7.15 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 12.8 Module Configuration The specific configuration for each EIC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 12-3. Module Configuration Feature EIC Number of external interrupts, including NMI 9 Table 12-4. Module Clock Name Module name Clock Name Description EIC CLK_EIC Peripheral Bus clock from the PBA clock domain Table 12-5.
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AT32UC3C 13. Frequency Meter (FREQM) Rev: 3.1.0.1 13.1 Features • • • • 13.2 Accurately measures a clock frequency Selectable reference clock A selectable clock can be measured Ratio can be measured with 24-bit accuracy Overview The Frequency Meter (FREQM) can be used to accurately measure the frequency of a clock by comparing it to a known reference clock. 13.3 Block Diagram Figure 13-1. Frequency Meter Block Diagram CLKSEL START CLK_MSR Counter VALUE CLK_REF Timer Trigger REFSEL 13.
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AT32UC3C 13.4.2 Clocks The clock for the FREQM bus interface (CLK_FREQM) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the FREQM before disabling the clock, to avoid freezing the FREQM ia an undefined state. A set of clocks can be selected as reference (CLK_REF) and another set of clocks can be selected for measurement (CLK_MSR).
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AT32UC3C • Write a zero to the MODE.REFCEN to disable he clock, without changing the other bits/fields in the Mode register. • Wait until the SR.RCLKBUSY bit reads as zero. 13.5.1.1 13.5.2 Cautionary note Note that if clock selected as source for CLK_REF is stopped during a measurement, this will not be detected by the FREQM. The BUSY bit in the STATUS register will never be cleared, and the DONE interrupt will never be triggered.
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AT32UC3C 13.6 User Interface Table 13-1.
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AT32UC3C 13.6.1 Name: Control Register CTRL Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - START • START Writing a zero to this bit has no effect. Writing a one to this bit will start a measurement.
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AT32UC3C 13.6.2 Name: Mode Register MODE Access Type: Read/Write Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 REFCEN - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 CLKSEL 12 11 10 9 8 2 1 0 REFNUM 7 6 5 4 3 - - - - - REFSEL • REFCEN: Reference Clock Enable 0: The reference clock is disabled 1: The reference clock is enabled • CLKSEL: Clock Source Selection Selects the source for CLK_MSR.
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AT32UC3C 13.6.3 Status Register Name: STATUS Access Type: Read-only Offset: 0x008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKBUSY BUSY • RCLKBUSY: FREQM Reference Clock Status 0: The FREQM ref clk is ready, so a measurement can start.
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AT32UC3C 13.6.4 Value Register Name: VALUE Access Type: Read-only Offset: 0x00C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] • VALUE: Result from measurement.
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AT32UC3C 13.6.5 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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AT32UC3C 13.6.6 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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AT32UC3C 13.6.7 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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AT32UC3C 13.6.8 Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x01C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending.
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AT32UC3C 13.6.9 Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x020 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE Writing a zero to a bit in this register has no effect.
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AT32UC3C 13.6.10 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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AT32UC3C 13.7 Module Configuration The specific configuration for each FREQM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 13-2. Module Clock Name Module Name FREQM Table 13-3.
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AT32UC3C Table 13-5.
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AT32UC3C 14. Peripheral Event Controller (PEVC) Rev: 1.0.0.0 14.1 Features • • • • 14.2 Direct peripheral to peripheral communication system Allows peripherals to receive, react to, and send peripheral events without CPU intervention Cycle deterministic event communication Asynchronous interrupts allow advanced peripheral operation in low power sleep modes Overview Many peripheral modules can be configured to emit or respond to signals known as peripheral events.
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AT32UC3C 14.
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AT32UC3C 14.4 I/O Lines Description Table 14-1. 14.5 I/O Lines Description Pin Name Pin Description Type PAD_EVT[n] External Event Inputs Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 14.5.1 I/O Lines Multiplexed I/O lines can be used as event generators. To generate a peripheral event from an external source the source pin must be configured as an input pin by the I/O Controller.
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AT32UC3C 14.6 Functional Description 14.6.1 14.6.1.1 PEVC Channel Operation PEVC routes incoming events to users by means of one channel per user. Channels operate in parallel, allowing multiple users to listen to the same generator. Channel Setup The Channel Multiplexer Register (CHMXn) is written to allocate a generator to a given channel. The Event Multiplexer field (EVMX) selects between the different generators, while the Software Event Multiplexer bit (SMX) selects Software Events.
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AT32UC3C 14.6.2 Event Shaper (EVS) Operation PEVC contains Event Shapers (EVS) for certain types of generators: • Asynchronous generators and/or external input • General-purpose waveforms like timer outputs or Generic Clocks Each Event Shaper is responsible of shaping one input, prior to going through a PEVC channel: • Synchronize asynchronous external inputs • Apply any additional glich-filtering • Detect rise, fall, or both edges of the incoming signal 14.6.2.
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AT32UC3C 14.
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AT32UC3C 14.7.1 Name: Version Register VERSION Access Type: Read-only Offset: 0x000 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Variant number of the module. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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AT32UC3C 14.7.2 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x004 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRIGOUT 23 22 21 20 EVMX 15 14 13 12 EVS 7 6 5 4 EVIN • TRIGOUT: Number of Trigger Outputs / Channels / Users Number of trigger outputs / channels implemented. No functionality associated. • EVMX: Number of Bits to control EVMX field in CHMXn Registers Number of Multiplexers control bits, derived from EVIN.
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AT32UC3C 14.7.3 Name: Input Glitch Filter Divider Register IGFDR Access Type: Read/Write Offset: 0x008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - IGFDR • IGFDR: Input Glitch Filter Divider Selects prescaler division ratio for the system RC clock used for glitch filtering.
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AT32UC3C 14.7.4 Name: Channel Status Register CHSR0 - CHSR1 Access Type: Read-only Offset: 0x010 - 0x014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHS 23 22 21 20 CHS 15 14 13 12 CHS 7 6 5 4 CHS • CHS: Channel Status 0: The corresponding channel is disabled. 1: The corresponding channel is enabled. This bit is cleared when the corresponding bit in CHDR is written to one.
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AT32UC3C 14.7.5 Name: Channel Enable Register CHER0 - CHER1 Access Type: Write-only Offset: 0x020 - 0x024 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHE 23 22 21 20 CHE 15 14 13 12 CHE 7 6 5 4 CHE • CHE: Channel Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in CHSR. Note: Channels 0 to 31 are controlled by CHER0. Channels 32 to 63 are controlled by CHER1.
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AT32UC3C 14.7.6 Name: Channel Disable Register CHDR0 - CHDR1 Access Type: Write-only Offset: 0x030 - 0x034 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHD 23 22 21 20 CHD 15 14 13 12 CHD 7 6 5 4 CHD • CHD: Channel Disable Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in CHSR. Note: Channels 0 to 31 are controlled by CHER0. Channels 32 to 63 are controlled by CHER1.
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AT32UC3C 14.7.7 Name: Software Event Register SEV0 - SEV1 Access Type: Write-only Offset: 0x040 - 0x044 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SEV 23 22 21 20 SEV 15 14 13 12 SEV 7 6 5 4 SEV • SEV: Software Event Writing a zero to this bit has no effect. Writing a one to this bit will trigger a Software Event for the corresponding channel. Note: Channels 0 to 31 are controlled by SEV0. Channels 32 to 63 are controlled by SEV1.
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AT32UC3C 14.7.8 Name: Channel / User Busy BUSY0 - BUSY1 Access Type: Read-only Offset: 0x050 - 0x054 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BUSY 23 22 21 20 BUSY 15 14 13 12 BUSY 7 6 5 4 BUSY • BUSY: Channel Status 0: The corresponding channel and user are idle. 1: The corresponding channel and user are busy. Note: Channels 0 to 31 are controlled by BUSY0. Channels 32 to 63 are controlled by BUSY1.
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AT32UC3C 14.7.9 Name: Trigger Status Register TRSR0 - TRSR1 Access Type: Read-only Offset: 0x060 - 0x064 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRS 23 22 21 20 TRS 15 14 13 12 TRS 7 6 5 4 TRS • TRS: Trigger Interrupt Status 0: An interrupt event has not occurred 1: An interrupt event has occurred This bit is cleared by writing a one to the corresponding bit in TRSCR. Note: Channels 0 to 31 are controlled by TRSR0.
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AT32UC3C 14.7.10 Name: Trigger Status Clear Register TRSCR0 - TRSCR1 Access Type: Write-only Offset: 0x070 - 0x074 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRSC 23 22 21 20 TRSC 15 14 13 12 TRSC 7 6 5 4 TRSC • TRSC: Trigger Interrupt Status Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in TRSR. Note: Channels 0 to 31 are controlled by TRSCR0.
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AT32UC3C 14.7.11 Name: Trigger Interrupt Mask Register TRIMR0 - TRIMR1 Access Type: Read-only Offset: 0x080 - 0x084 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRIM 23 22 21 20 TRIM 15 14 13 12 TRIM 7 6 5 4 TRIM • TRIM: Trigger Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in TRIDR is written to one.
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AT32UC3C 14.7.12 Name: Trigger Interrupt Enable Register TRIER0 - TRIER1 Access Type: Write-only Offset: 0x090 - 0x094 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRIE 23 22 21 20 TRIE 15 14 13 12 TRIE 7 6 5 4 TRIE • TRIE: Trigger Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in TRIMR. Note: Channels 0 to 31 are controlled by TRIER0.
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AT32UC3C 14.7.13 Name: Trigger Interrupt Disable Register TRIDR0 - TRIDR1 Access Type: Write-only Offset: 0x0A0 - 0x0A4 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRID 23 22 21 20 TRID 15 14 13 12 TRID 7 6 5 4 TRID • TRID: Trigger Interrupt Disable Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR. Note: Channels 0 to 31 are controlled by TRIDR0.
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AT32UC3C 14.7.14 Name: Overrun Status Register OVSR0 - OVSR1 Access Type: Read-only Offset: 0x0B0 - 0x0B4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVS 23 22 21 20 OVS 15 14 13 12 OVS 7 6 5 4 OVS • OVS: Overrun Interrupt Status 0: An interrupt event has not occurred 1: An interrupt event has occurred This bit is cleared by writing a one to the corresponding bit in OVSCR. Note: Channels 0 to 31 are controlled by OVSR0.
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AT32UC3C 14.7.15 Name: Overrun Status Clear Register OVSCR0 - OVSCR1 Access Type: Write-only Offset: 0x0C0 - 0x0C4 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVSC 23 22 21 20 OVSC 15 14 13 12 OVSC 7 6 5 4 OVSC • OVSC: Overrun Interrupt Status Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in OVSR. Note: Channels 0 to 31 are controlled by OVSCR0.
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AT32UC3C 14.7.16 Name: Overrun Interrupt Mask Register OVIMR0 - OVIMR1 Access Type: Read-only Offset: 0x0D0 - 0x0D4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVIM 23 22 21 20 OVIM 15 14 13 12 OVIM 7 6 5 4 OVIM • OVIM: Overrun Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in OVIDR is written to one.
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AT32UC3C 14.7.17 Name: Overrun Interrupt Enable Register OVIER0 - OVIER1 Access Type: Write-only Offset: 0x0E0 - 0x0E4 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVIE 23 22 21 20 OVIE 15 14 13 12 OVIE 7 6 5 4 OVIE • OVIE: Overrun Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in OVIMR. Note: Channels 0 to 31 are controlled by OVIER0.
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AT32UC3C 14.7.18 Name: Overrun Interrupt Disable Register OVIDR0 - OVIDR1 Access Type: Write-only Offset: 0x0F0 - 0x0F4 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVID 23 22 21 20 OVID 15 14 13 12 OVID 7 6 5 4 OVID • OVID: Overrun Interrupt Disable Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR. Note: Channels 0 to 31 are controlled by OVIDR0.
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AT32UC3C 14.7.19 Name: Channel Multiplexer Register CHMXn Access Type: Read/Write Offset: 0x100 + n*0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - SMX 7 6 5 4 3 2 1 0 - - EVMX • EVMX: Event Multiplexer Select input event / generator. • SMX: Software Event Multiplexer 0: The Software Event is not selected. Event / generator is selected by EVMX.
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AT32UC3C 14.7.20 Name: Event Shaper Register EVSm Access Type: Read/Write Offset: 0x200 + m*0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - IGF EVF EVR • EVR: Event Rise 0: No event detection on rising edge. 1: Event detection on rising edge. • EVF: Event Fall 0: No event detection on falling edge.
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AT32UC3C 14.8 Module Configuration The specific configuration for each PEVC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 14-3. Module Configuration Feature Parameter PEVC Number of Generators EVIN 34 Number of Event Shapers EVS 24 Number of Channels / Users TRIGOUT 22 Table 14-4.
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AT32UC3C Table 14-6. PEVC event numbers Event Number (EVMx) Event Generator - Event source 26 ACIFA1 - event 0 27 ACIFA1 - event 1 28 AST - alarm event 0 29 AST - period event 0 30 PWM - compare match on event 0 31 PWM - compare match on event 1 32 QDEC0 - compare match 33 QDEC1 - compare match Event Shaper The following tables defines the triggered action for each PEVC channel. Table 14-7.
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AT32UC3C 15. Flash Controller (FLASHC) Rev: 3.0.2.2 15.1 Features • Controls flash block with dual read ports allowing staggered reads. • Supports 0 and 1 wait state bus access. • Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per clock cycle. • 32-bit HSB interface for reads from flash array and writes to page buffer. • 32-bit PB interface for issuing commands to and configuration of the controller.
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AT32UC3C 15.3.4 15.4 15.4.1 Debug Operation When an external debugger forces the CPU into debug mode, the FLASHC continues normal operation. If the FLASHC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.
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AT32UC3C The FLASHC can also operate in systems where the HSB bus clock period is faster than the access speed of the flash memory. Wait state support and a read granularity of 64 bits ensure efficiency in such systems. Performance for systems with high clock frequency is increased since the flash internally is configured as two separate banks of 32 bits. Each bank has its own read port. In 0ws mode, only one of the two flash read ports is accessed. The other flash read port is idle.
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AT32UC3C Figure 15-1. Memory Map for the Flash Memories2 Offset from base address 0x0080 0200 Factory Page User Page REserved 0x0080 0000 Flash data array pw 0 Flash base address Flash with extra pages All addresses are byte addresses 15.4.6 High Speed Read Mode The flash provides a High Speed Read Mode, offering slightly higher flash read speed at the cost of higher power consumption.
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AT32UC3C Figure 15-2. High Speed Mode Frequency 1 wait state 0 wait state Frequency limit for 0 wait state operation Speed mode h ig al m or H N 15.4.7 Quick Page Read A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed page. All bits in all words in this page are AND’ed together, returning a 1-bit result. This result is placed in the Quick Page Read Result (QPRR) bit in Flash Status Register (FSR).
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AT32UC3C Figure 15-3.
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AT32UC3C 1. Clear page buffer 2. Write to the page buffer the result of the logical bitwise AND operation between the contents of the flash page and the new data to write. Only bits that were in an erased state can be changed from the original page. 3. Write Page. 15.5 Flash Commands The FLASHC offers a command set to manage programming of the flash memory, locking and unlocking of regions, and full flash erasing. See Section 15.8.2 for a complete list of commands.
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AT32UC3C After programming, the page can be locked to prevent miscellaneous write or erase sequences. Locking is performed on a per-region basis, so locking a region locks all pages inside the region. Additional protection is provided for the lowermost address space of the flash. This address space is allocated for the Boot Loader, and is protected both by the lock bit(s) corresponding to this address space, and the BOOTPROT[2:0] fuses. Data to be written are stored in an internal buffer called page buffer.
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AT32UC3C • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. • Lock Error: At least one lock region is protected, or BOOTPROT is different from 0. The erase command has been aborted and no page has been erased. A “Unlock region containing given page” (UP) command must be executed to unlock any locked regions. 15.5.3 Region Lock Bits The flash memory has p pages, and these pages are grouped into 16 lock regions, each region containing p/16 pages.
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AT32UC3C through a dedicated Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions.: Table 15-2. General-purpose Fuses with Special Functions Generalpurpose fuse number Name Usage 15:0 LOCK Region lock bits. EPFL External Privileged Fetch Lock. Used to prevent the CPU from fetching instructions from external memories when in privileged mode. This bit can only be changed when the security bit is cleared.
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AT32UC3C The BOOTPROT fuses protects the following address space for the Boot Loader: Table 15-3. Boot Loader Area Specified by BOOTPROT BOOTPROT Pages protected by BOOTPROT Size of protected memory 7 None 0 6 0-1 1kByte 5 0-3 2kByte 4 0-7 4kByte 3 0-15 8kByte 2 0-31 16kByte 1 0-63 32kByte 0 0-127 64kByte The SECURE fuses have the following functionality: Table 15-4.
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AT32UC3C The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that the 16 lowest general-purpose fuse bits can also be written/erased using the commands for locking/unlocking regions, see Section 15.5.3. 15.7 Security bit The security bit allows the entire chip to be locked from external JTAG or other debug access for code security. The security bit can be written by a dedicated command, Set Security Bit (SSB).
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AT32UC3C 15.8 User interface Table 15-5.
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AT32UC3C 15.8.1 Name: Flash Control Register FCR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - FWS - - PROGE LOCKE - FRDY • FWS: Flash Wait State 0: The flash is read with 0 wait states. 1: The flash is read with 1 wait state.
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AT32UC3C 15.8.2 Name: Flash Command Register FCMD Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 The FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to be ignored, and the PROGE bit to be set.
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AT32UC3C Table 15-6. Semantic of PAGEN Field in Different Commands Command PAGEN description Program GP Fuse Byte WriteData[7:0], ByteAddress[2:0] Erase All GP Fuses Not used Quick Page Read Page number Write User Page Not used Erase User Page Not used Quick Page Read User Page Not used High Speed Mode Enable Not used High Speed Mode Disable Not used • CMD: Command This field defines the flash command.
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AT32UC3C 15.8.3 Name: Flash Status Register FSR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 LOCK15 LOCK14 LOCK13 LOCK12 LOCK11 LOCK10 LOCK9 LOCK8 23 22 21 20 19 18 17 16 LOCK7 LOCK6 LOCK5 LOCK4 LOCK3 LOCK2 LOCK1 LOCK0 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - HSMODE QPRR SECURITY PROGE LOCKE - FRDY • LOCKx: Lock Region x Lock Status 0: The corresponding lock region is not locked.
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AT32UC3C 15.8.4 Name: Parameter Register PR Access Type: Read-only Offset: 0x0C Reset Value: 0x00000000(*) 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - 7 6 5 4 3 - - - - PSZ 2 1 0 FSZ • FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 15-8.
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AT32UC3C • PSZ: Page Size The size of a flash page. Table 15-9.
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AT32UC3C 15.8.5 Name: Version Register VR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000(*) 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8]- 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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AT32UC3C 15.8.
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AT32UC3C 15.8.
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AT32UC3C 15.9 Fuses Settings The flash block contains 32 general purpose fuses. These 32 fuses can be found in the Flash General Purpose Fuse Register Low. Some of these fuses have defined meanings outside the flash controller and are described in this section. In addition to the General Purpose fuses parts of the Flash, user page can have a defined meaning outside the flash controller and are described in this section.
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AT32UC3C • BODHYST: 1.8V Brown Out Detector Hysteresis 0: The BOD18 hysteresis is disabled. 1: The BOD18 hysteresis is enabled. • BODLEVEL: 1.8V Brown Out Detector Trigger Level This controls the voltage trigger level for the BOD18. When the flash fuse calibration is done (SCIF.BOD.FCD is set): SCIF.BOD.LEVEL is loaded to 0x28 if the BODLEVEL fuses are greater than 0xA. SCIF.BOD.LEVEL is loaded to (BODLEVEL x 4) if the BODLEVEL fuses are lower or equal to 0xA.
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AT32UC3C 15.9.3 Fuses in User Page (address 0x80800000) 15.9.3.1 First word (address 0x80800000) Table 15-13. User Page Fuse Description 31 30 29 28 WDTDISRV 23 27 26 25 24 18 17 16 10 9 8 2 1 0 SS_ADRR[14:8] 22 21 20 19 SS_ADRR[7:0] 15 14 13 12 11 SS_ADRF[15:8] 7 6 5 4 3 SS_ADRF[7:0] • SS_ADRR: Size of the CPU RAM controlled by the Secure State The section of the CPU RAM controlled by the Secure State is from address 0x00000000 to address (SS_ADRR << 10).
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AT32UC3C 15.10 Calibration Settings Some analog blocks require to be calibrated. The recommended calibration settings are written in the factory page. The base address of the factory page is 0x80800200. Table 15-14.
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AT32UC3C 15.10.0.1 Oscillator Calibration (offset 0x0000) Table 15-15. 31 Oscillator Calibration 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 RC1M_CALIB_5V[7:0] 23 22 21 20 19 RC8M_CALIB_5V[7:0] 15 14 13 12 11 RC1M_CALIB[7:0] 7 6 5 4 3 RC8M_CALIB[7:0] • RC1M_CALIB_5V: Calibration of RC8M operating at 1MHz and at 5V This calibration should be used when the RC8M is used at a frequency of 1 MHz and when the voltage of the VDDIN_5 pin is within [4.5V:5.5V].
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AT32UC3C 15.10.0.2 ADC Core Calibration (offset 0x0004) Table 15-16. ADC Core Calibration 31 30 29 28 27 - - 23 22 21 20 19 - - - - 15 14 13 12 26 25 24 18 17 16 - - - - 11 10 9 8 2 1 0 ADC_OCAL[5:0] ADC_GCAL[14:8] 7 6 5 4 3 ADC_GCAL[7:0] • ADC_OCAL: Offset Calibration of the ADC core This value should be written to the ADCCAL.OCAL field of the ADCIFA module. • ADC_GCAL: Gain Calibration of the ADC core This value should be written to the ADCCAL.
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AT32UC3C 15.10.0.3 ADC S/H Calibration (offset 0x0008) Table 15-17. ADC S/H Calibration 31 30 29 28 27 26 25 24 - - - - - - 23 22 21 20 19 18 17 16 9 8 ADC_GAIN1[9:8] ADC_GAIN1[7:0] 15 14 13 12 11 10 - - - - - - ADC_GAIN0[9:8] 7 6 5 4 3 2 1 0 ADC_GAIN0[7:0] • ADC_GAIN1: Gain Calibration of the ADC S/H1 This value should be written to the SHCAL.GAIN1 field of the ADCIFA module.
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AT32UC3C 15.10.0.4 DAC0 Channel Calibration (offset 0x000C (DAC0 Channel A), 0x0010 (DAC0 Channel B)), Table 15-18. DAC0A and DAC0B Channel Calibration 31 30 29 28 27 26 25 24 - - - - - - - DAC_GCAL[8] 23 22 21 20 19 18 17 16 DAC_GCAL[7:0] 15 14 13 12 11 10 9 8 - - - - - - - DAC_OCAL[8] 7 6 5 4 3 2 1 0 DAC_OCAL[7:0] • DAC_GCAL: Gain Calibration of the DAC Channel This value should be written to the GOC.GCR field of the DACIFB0 module.
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AT32UC3C 15.10.0.5 DAC1 Channel Calibration (offset 0x0014 (DAC1 Channel A), 0x0018 (DAC1 Channel B)), Table 15-19. DAC1A and DAC1B Channel Calibration 31 30 29 28 27 26 25 24 - - - - - - - DAC_GCAL[8] 23 22 21 20 19 18 17 16 DAC_GCAL1[7:0] 15 14 13 12 11 10 9 8 - - - - - - - DAC_OCAL[8] 7 6 5 4 3 2 1 0 DAC_OCAL[7:0] • DAC_GCAL: Gain Calibration of the DAC Channel This value should be written to the GOC.GCR field of the DACIFB1 module.
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AT32UC3C 15.11 Serial Number Each device has a unique 120 bits serial number readable from address 0x80800284 to 0x80800292. 15.12 Module Configuration The specific configuration for each FLASHC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 15-20.
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AT32UC3C 16. HSB Bus Matrix (HMATRIXB) Rev: 1.3.0.3 16.1 Features • • • • • • • • • 16.
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AT32UC3C To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR.
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AT32UC3C • Undefined Length Burst Arbitration In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as a defined length burst transfer and can be selected among the following five possibilities: 1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will never be broken. 2.
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AT32UC3C rent transfer, if no other master request is pending, the slave remains connected to the last master that performed the access. Other non privileged masters still get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform single accesses. • Round-Robin Arbitration with Fixed Default Master This is another biased round-robin algorithm.
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AT32UC3C 16.5 User Interface Table 16-1.
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AT32UC3C Table 16-1.
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AT32UC3C Table 16-1.
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AT32UC3C 16.5.1 Name: Master Configuration Registers MCFG0...MCFG15 Access Type: Read/Write Offset: 0x00 - 0x3C Reset Value: 0x00000002 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – ULBT • ULBT: Undefined Length Burst Type Table 16-2.
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AT32UC3C 16.5.2 Name: Slave Configuration Registers SCFG0...
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AT32UC3C 16.5.3 Bus Matrix Priority Registers A For Slaves Register Name: PRAS0...PRAS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 - - 23 22 - - 15 14 - - 7 6 - - 29 28 M7PR 21 20 M5PR 13 12 M3PR 5 4 M1PR 27 26 - - 19 18 - - 11 10 - - 3 2 - - 25 24 M6PR 17 16 M4PR 9 8 M2PR 1 0 M0PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
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AT32UC3C 16.5.4 Name: Priority Registers B For Slaves PRBS0...PRBS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 - - 23 22 - - 15 14 - - 7 6 - - 29 28 M15PR 21 20 M13PR 13 12 M11PR 5 4 M9PR 27 26 - - 19 18 - - 11 10 - - 3 2 - - 25 24 M14PR 17 16 M12PR 9 8 M10PR 1 0 M8PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
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AT32UC3C 16.5.5 Name: Special Function Registers SFR0...SFR15 Access Type: Read/Write Offset: 0x110 - 0x14C Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SFR 23 22 21 20 SFR 15 14 13 12 SFR 7 6 5 4 SFR • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those will be defined where they are used.
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AT32UC3C 16.6 Bus Matrix Connections Accesses to unused areas returns an error result to the master requesting such an access. The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing a different memory mapping per master. The master number in the table below can be used to index the HMATRIX control registers. For example, MCFG0 is associated with the CPU Data master interface. Table 16-3.
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AT32UC3C HMATRIX MASTERS CPU Data 0 CPU Instruction 1 CPU SAB 2 SAU 3 PDCA 4 MDMA Read 5 MDMA Write 6 USBC 7 CANIF 8 MACB 9 Internal Flash HSB-PB Bridge A HSB-PB Bridge B HSB-PB Bridge C Internal SRAM HSB SRAM EBI SAU Figure 16-1.
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AT32UC3C 17. External Bus Interface (EBI) Rev.: 1.7.0.2 17.
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AT32UC3C 17.3 Block Diagram Figure 17-1. EBI Block Diagram INTC SDRAMC_irq EBI HMATRIX HSB SDRAM Controller DATA[15:0] NWE1 NWE0 Static Memory Controller NRD NCS[3:0] ADDR[23:0] MUX Logic SFR registers I/O Controller CAS RAS SDA10 SDWE Address Decoders Chip Select Assignor SDCK SDCKE NWAIT HSB-PB Bridge Peripheral Bus 17.
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AT32UC3C Table 17-1.
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AT32UC3C 17.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 17.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O Controller lines. The user must first configure the I/O Controller to assign the EBI pins to their peripheral functions. 17.5.2 Power Management To prevent bus errors EBI operation must be terminated before entering sleep mode. 17.5.
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AT32UC3C 17.6 Functional Description The EBI transfers data between the internal HSB bus (handled by the HMATRIX) and the external memories or peripheral devices.
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AT32UC3C Table 17-4. EBI Pins and External Static Devices Connections (Continued) Pins of the Interfaced Device 8-bit Static Device Pins name 2 x 8-bit Static Devices Controller SMC NRD OE NWE0 WE NWE1 Note: 16-bit Static Device – OE OE WE (1) WE WE (1) NBS1(2) 1. NWE1 enables upper byte writes. NWE0 enables lower byte writes. 2. NBS1 enables upper byte writes. NBS0 enables lower byte writes. Table 17-5.
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AT32UC3C 17.7.2 Connection Examples Figure 17-2 on page 306shows an example of connections between the EBI and external devices. Figure 17-2.
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AT32UC3C 18. Static Memory Controller (SMC) Rev. 1.0.6.5 18.1 Features • • • • • • • • • • • • 18.
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AT32UC3C 18.3 Block Diagram Figure 18-1. SMC Block Diagram (AD_MSB=23) NCS[5:0] HMatrix NCS[5:0] NRD SMC Chip Select NRD NWR0/NWE NWE0 A0/NBS0 ADDR[0] NWR1/NBS1 SMC Power Manager A1/NWR2/NBS2 CLK_SMC NWE1 EBI Mux Logic A[AD_MSB:2] D[15:0] NWAIT I/O Controller ADDR[1] ADDR[AD_MSB:2] DATA[15:0] NWAIT User Interface Peripheral Bus 18.4 I/O Lines Description Table 18-1. 18.
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AT32UC3C 18.5.1 I/O Lines The SMC signals pass through the External Bus Interface (EBI) module where they are multiplexed. The user must first configure the I/O Controller to assign the EBI pins corresponding to SMC signals to their peripheral function. If the I/O lines of the EBI corresponding to SMC signals are not used by the application, they can be used for other purposes by the I/O Controller. 18.5.2 Clocks The clock for the SMC bus interface (CLK_SMC) is generated by the Power Manager.
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AT32UC3C Figure 18-3. Memory Connections for Six External Devices NCS[0] - NCS[5] NRD SMC NWE NCS5 A[AD_MSB:0] NCS4 D[15:0] NCS3 NCS2 NCS1 NCS0 Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable 8 or 16 18.6.3 18.6.3.1 A[AD_MSB:0] D[15:0] or D[7:0] Connection to External Devices Data bus width A data bus width of 8 or 16 bits can be selected for each chip select.
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AT32UC3C Figure 18-5. Memory Connection for a 16-bit Data Bus D[15:0] D[15:0] A[19:2] A[18:1] A1 SMC A[0] NBS0 Low Byte Enable NBS1 High Byte Enable NWE Write Enable NRD Output Enable NCS[2] Memory Enable •Byte write access The byte write access mode supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in byte write access mode.
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AT32UC3C Figure 18-6. Connection of two 8-bit Devices on a 16-bit Bus: Byte Write Option D[7:0] D[7:0] D[15:8] A[24:2] SMC A[23:1] A[0] A1 NWR0 Write Enable NWR1 NRD Read Enable Memory Enable NCS[3] D[15:8] A[23:1] A[0] Write Enable Read Enable Memory Enable •Signal multiplexing Depending on the MODE.BAT bit, only the write signals or the byte select signals are used. To save I/Os at the external bus interface, control signals at the SMC interface are multiplexed.
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AT32UC3C access type. NWR0 to NWR1 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..3] chip select lines. 18.6.4.1 Read waveforms The read cycle is shown on Figure 18-7 on page 313. The read cycle starts with the address setting on the memory address bus, i.e.: {A[23:2], A1, A0} for 8-bit devices {A[23:2], A1} for 16-bit devices Figure 18-7.
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AT32UC3C 1. NCSRDSETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCSRDPULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge. 3. NCSRDHOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. •Read cycle The NRDCYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change.
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AT32UC3C Figure 18-8. No Setup, No Hold on NRD, and NCS Read Signals CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NRD NCS D[15:0] NRDSETUP NRDPULSE NRDPULSE NCSRDPULSE NCSRDPULSE NCSRDPULSE NRDCYCLE NRDCYCLE NRDCYCLE • Null Pulse Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads to unpredictable behavior. 18.6.4.
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AT32UC3C Figure 18-9. READMODE = 1: Data Is Sampled by SMC Before the Rising Edge of NRD CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NRD NCS tPACC D[15:0] Data Sampling •Read is controlled by NCS (MODE.READMODE = 0) Figure 18-10 on page 317 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the MODE.
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AT32UC3C Figure 18-10. READMODE = 0: Data Is Sampled by SMC Before the Rising Edge of NCS CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NRD NCS tPACC D[15:0] Data Sampling 18.6.4.3 Write waveforms The write protocol is similar to the read protocol. It is depicted in Figure 18-11 on page 318. The write cycle starts with the address setting on the memory address bus. •NWE waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1.
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AT32UC3C Figure 18-11. Write Cycle CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NWE NCS NWESETUP NCSWRSETUP NWEPULSE NCSWRPULSE NWEHOLD NCSWRHOLD NWECYCLE •Write cycle The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change.
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AT32UC3C •Null delay setup and hold If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 18-12 on page 319). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed. Figure 18-12.
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AT32UC3C Figure 18-13. WRITEMODE = 1. The Write Operation Is Controlled by NWE CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 NCS D[15:0] •Write is controlled by NCS (MODE.WRITEMODE = 0) Figure 18-14 on page 320 shows the waveforms of a write operation with MODE.WRITEMODE written to zero. The data is put on the bus during the pulse and hold steps of the NCS signal.
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AT32UC3C 18.6.4.6 Coding timing parameters All timing parameters are defined for one chip select and are grouped together in one register according to their type. The Setup register (SETUP) groups the definition of all setup parameters: • NRDSETUP, NCSRDSETUP, NWESETUP, and NCSWRSETUP. The Pulse register (PULSE) groups the definition of all pulse parameters: • NRDPULSE, NCSRDPULSE, NWEPULSE, and NCSWRPULSE. The Cycle register (CYCLE) groups the definition of all cycle parameters: • NRDCYCLE, NWECYCLE.
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AT32UC3C 18.6.5 18.6.5.1 Automatic Wait States Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict. Chip select wait states The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the deactivation of one device and the activation of the next one.
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AT32UC3C An early read wait state is automatically inserted if at least one of the following conditions is valid: • if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 18-16 on page 323). • in NCS write controlled mode (MODE.WRITEMODE = 0), if there is no hold timing on the NCS signal and the NCSRDSETUP parameter is set to zero, regardless of the read mode (Figure 18-17 on page 324). The write operation must end with a NCS rising edge.
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AT32UC3C Figure 18-17. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No Setup.
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AT32UC3C Figure 18-18. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle. CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 Internal write controlling signal external write controlling signal(NWE) No hold Read setup=1 NRD D[15:0] Write cycle (WRITEMODE = 1) 18.6.5.3 Early Read Wait State Read cycle (READMODE=0 or READMODE=1) Reload user configuration wait state The user may change any of the configuration parameters by writing the SMC user interface.
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AT32UC3C •Slow clock mode transition A reload configuration wait state is also inserted when the slow clock mode is entered or exited, after the end of the current transfer (see Section 18.6.8). 18.6.5.4 Read to write wait state Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document.
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AT32UC3C Figure 18-19. TDF Period in NRD Controlled Read Access (TDFCYCLES = 2) CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NRD NCS D[15:0] tPACC TDF = 2 clock cycles NRD controlled read operation Figure 18-20.
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AT32UC3C 18.6.6.2 TDF optimization enabled (MODE.TDFMODE = 1) When the MODE.TDFMODE bit is written to one (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 18-21 on page 328 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0.
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AT32UC3C • read access followed by a write access on the same chip select. with no TDF optimization. Figure 18-22. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Two Read Accesses on Different Chip Selects.
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AT32UC3C Figure 18-24. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Read and Write accesses on the Same Chip Select. CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 Read1 controlling signal(NRD) Write2 setup = 1 Read1 hold = 1 Write2 controlling signal(NWE) TDFCYCLES = 5 D[15:0] 4 TDF WAIT STATES Read1 cycle TDFCYCLES = 5 18.6.
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AT32UC3C The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 18-26 on page 332. Figure 18-25. Write Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2).
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AT32UC3C Figure 18-26. Read Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2).
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AT32UC3C 18.6.7.3 Ready mode In Ready mode (MODE.EXNWMODE = 3), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 18-27 on page 333 and Figure 18-28 on page 334. After deassertion, the access is completed: the hold step of the access is performed.
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AT32UC3C Figure 18-28. NWAIT Assertion in Read Access: Ready Mode (EXNWMODE = 3).
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AT32UC3C 18.6.7.4 NWAIT latency and read/write timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the two cycles of resynchronization plus one cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
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AT32UC3C 18.6.8 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the SMC’s Power Management Controller is asserted because CLK_SMC has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied.
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AT32UC3C 18.6.8.2 Switching from (to) slow clock mode to (from) normal mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters. See Figure 18-31 on page 337. The external device may not be fast enough to support such timings. Figure 18-32 on page 338 illustrates the recommended procedure to properly switch from one mode to the other. Figure 18-31.
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AT32UC3C Figure 18-32. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode Internal signal from PM CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NWE 1 1 1 2 3 2 NCS SLOW CLOCK MODE WRITE NORMAL MODE WRITE IDLE STATE Reload Configuration Wait State 18.6.9 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the Page Mode Enabled bit is written to one in the MODE register (MODE.PMEN).
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AT32UC3C Figure 18-33. Page Mode Read Protocol (Address MSB and LSB Are Defined in Table 18-6 on page 338) CLK_SMC A[MSB] A[LSB] NRD tpa tsa NCS tsa D[15:0] NCSRDPULSE NRDPULSE NRDPULSE The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first access to the page is defined with the PULSE.NCSRDPULSE field value.
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AT32UC3C 18.6.9.3 Page mode restriction The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may lead to unpredictable behavior. 18.6.9.4 Sequential and non-sequential accesses If the chip select and the MSB of addresses as defined in Table 18-6 on page 338 are identical, then the current access lies in the same page as the previous one, and no page break occurs.
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AT32UC3C 18.7 User Interface The SMC is programmed using the registers listed in Table 18-8 on page 341. For each chip select, a set of four registers is used to program the parameters of the external device connected on it. In Table 18-8 on page 341, “CS_number” denotes the chip select number. Sixteen bytes (0x10) are required per chip select. The user must complete writing the configuration by writing anyone of the Mode Registers. Table 18-8.
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AT32UC3C 18.7.
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AT32UC3C 18.7.
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AT32UC3C 18.7.3 Cycle Register Register Name: CYCLE Access Type: Read/Write Offset: 0x08 + CS_number*0x10 Reset Value: 0x00030003 31 30 29 28 27 26 25 24 – – – – – – – NRDCYCLE[8] 23 22 21 20 19 18 17 16 NRDCYCLE[7:0] 15 14 13 12 11 10 9 8 – – – – – – – NWECYCLE[8] 7 6 5 4 3 2 1 0 NWECYCLE[7:0] • NRDCYCLE[8:0]: Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle.
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AT32UC3C 18.7.4 Mode Register Register Name: MODE Access Type: Read/Write Offset: 0x0C + CS_number*0x10 Reset Value: 0x10002103 31 30 29 28 – – 23 22 21 20 – – – TDFMODE 15 14 13 12 – – 7 6 – – PS DBW 5 4 EXNWMODE 27 26 25 24 – – – PMEN 19 18 17 16 TDFCYCLES 11 10 9 8 – – – BAT 3 2 1 0 – – WRITEMODE READMODE • PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes.
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AT32UC3C • DBW: Data Bus Width DBW Data Bus Width 0 8-bit bus 1 16-bit bus 2 Reserved 3 Reserved • BAT: Byte Access Type This field is used only if DBW defines a 16-bit data bus.
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AT32UC3C • READMODE: Read Mode READMODE Read Access Mode 0 The read operation is controlled by the NCS signal. If TDF are programmed, the external bus is marked busy after the rising edge of NCS. If TDF optimization is enabled (TDFMODE = 1), TDF wait states are inserted after the setup of NCS. 1 The read operation is controlled by the NRD signal. If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
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AT32UC3C 19. SDRAM Controller (SDRAMC) Rev: 2.2.0.4 19.1 Features • 128-Mbytes address space • Numerous configurations supported • • • • • • 19.
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AT32UC3C 19.3 Block Diagram Figure 19-1.
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AT32UC3C Table 19-1. 19.5 19.5.1 I/O Lines Description Name Description Type Active Level DQM[1:0] Data Mask Enable Signals Output High SDRAMC_A[12:0] Address Bus Output D[15:0] Data Bus Input/Output Application Example Hardware Interface Figure 19-2 on page 350 shows an example of SDRAM device connection using a 16-bit data bus width.
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AT32UC3C 19.5.2.1 16-bit memory data bus width Table 19-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 BA[1:0] 13 12 11 10 9 8 7 6 Row[10:0] BA[1:0] BA[1:0] 5 4 3 2 1 Column[7:0] Row[10:0] M0 Column[9:0] Row[10:0] 0 M0 Column[8:0] Row[10:0] BA[1:0] Table 19-3.
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AT32UC3C 19.6.3 Clocks The clock for the SDRAMC bus interface (CLK_SDRAMC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the SDRAMC before disabling the clock, to avoid freezing the SDRAMC in an undefined state. 19.6.4 Interrupts The SDRAMC interrupt request line is connected to the interrupt controller. Using the SDRAMC interrupt requires the interrupt controller to be programmed first. 19.7 19.7.
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AT32UC3C quency, the TR register must be written with the value 1562 (15.625 µs x 100 MHz) or 781 (7.81 µs x 100 MHz). After initialization, the SDRAM devices are fully functional. Figure 19-3. SDRAM Device Initialization Sequence SDCKE tRP tRC tMRD SDCK SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE DQM Inputs Stable for 200 usec 19.7.
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AT32UC3C Figure 19-4. Write Burst, 16-bit SDRAM Access tRCD = 3 SDCS SDCK SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f Col g Col h Col i Col j Col k Col l Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl RAS CAS SDWE D[15:0] 19.7.3 Dna SDRAM Controller Read Cycle The SDRAMC allows burst access, incremental burst of unspecified length or single access. In all cases, the SDRAMC keeps track of the active row in each bank, thus maximizing performance of the SDRAM.
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AT32UC3C Figure 19-5. Read Burst, 16-bit SDRAM Access tRCD = 3 CAS = 2 SDCS SDCK SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f RAS CAS SDWE D[15:0] (Input) 19.7.4 Dna Dnb Dnc Dnd Dne Dnf Border Management When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAMC generates a precharge command, activates the new row and initiates a read or write command.
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AT32UC3C Figure 19-6. Read Burst with Boundary Row Access TRP = 3 CAS = 2 TRCD = 3 SDCS SDCK Row n SDRAMC_A[12:0] Col a Col b Col c Col d Row m Col a Col b Col c Col d Col e RAS CAS SDWE D[15:0] 19.7.5 Dna Dnb Dnc Dnd Dma Dmb Dmc Dmd Dme SDRAM Controller Refresh Cycles An auto refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto refresh automatically.
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AT32UC3C Figure 19-7. Refresh Cycle Followed by a Read Access tRP = 3 tRC = 8 tRCD = 3 CAS = 2 SDCS SDCK Row n Col c Col d SDRAMC_A[12:0] Row m Col a RAS CAS SDWE D[15:0] (input) 19.7.6 Dnb Dnc Dnd Dma Power Management Three low power modes are available: • Self refresh mode: the SDRAM executes its own auto refresh cycles without control of the SDRAMC. Current drained by the SDRAM is very low. • Power-down mode: auto refresh cycles are controlled by the SDRAMC.
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AT32UC3C and Drive Strength (DS) parameters must be set by writing the corresponding fields in the LPR register, and transmitted to the low power SDRAM device during initialization. After initialization, as soon as the LPR.PASR, LPR.DS, or LPR.TCSR fields are modified and self refresh mode is activated, the SDRAMC issues an Extended Load Mode Register command to the SDRAM and the Extended Mode Register of the SDRAM device is accessed automatically.
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AT32UC3C Figure 19-9. Low Power Mode Behavior TRCD = 3 CAS = 2 Low Power Mode SDCS SDCK SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f RAS CAS SDCKE D[15:0] (input) 19.7.6.3 Dna Dnb Dnc Dnd Dne Dnf Deep power-down mode This mode is selected by writing the value three to the LPR.LPCB field. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost.
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AT32UC3C Figure 19-10.
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AT32UC3C 19.8 User Interface Table 19-5.
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AT32UC3C 19.8.1 Mode Register Register Name: MR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - MODE • MODE: Command Mode This field defines the command issued by the SDRAMC when the SDRAM device is accessed. MODE Description 0 Normal mode.
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AT32UC3C 19.8.2 Refresh Timer Register Register Name: TR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 1 0 COUNT[11:8] 3 2 COUNT[7:0] • COUNT[11:0]: Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated.
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AT32UC3C 19.8.3 Configuration Register Register Name: CR Access Type: Read/Write Offset: 0x08 Reset Value: 0x852372C0 31 30 29 28 27 26 TXSR 23 22 21 14 20 19 18 13 DBW 6 16 12 11 10 9 8 1 0 TWR 5 CAS 17 TRP TRC 7 24 TRAS TRCD 15 25 4 NB 3 2 NR NC • TXSR: Exit Self Refresh to Active Delay Reset value is eight cycles. This field defines the delay between SCKE set high and an Activate command in number of cycles. Number of cycles is between 0 and 15.
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AT32UC3C • CAS: CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles is managed. CAS CAS Latency (Cycles) 0 Reserved 1 1 2 2 3 3 • NB: Number of Banks Reset value is two banks. NB Number of Banks 0 2 1 4 • NR: Number of Row Bits Reset value is 11 row bits. NR Row Bits 0 11 1 12 2 13 3 Reserved • NC: Number of Column Bits Reset value is 8 column bits.
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AT32UC3C 19.8.4 High Speed Register Register Name: HSR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DA • DA: Decode Cycle Enable A decode cycle can be added on the addresses as soon as a non-sequential access is performed on the HSB bus.
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AT32UC3C 19.8.
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AT32UC3C • LPCB: Low Power Configuration Bits LPCB Low Power Configuration 0 Low power feature is inhibited: no power-down, self refresh or deep power-down command is issued to the SDRAM device. 1 The SDRAMC issues a self refresh command to the SDRAM device, the SDCLK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access.
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AT32UC3C 19.8.6 Interrupt Enable Register Register Name: IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - RES Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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AT32UC3C 19.8.7 Interrupt Disable Register Register Name: IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - RES Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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AT32UC3C 19.8.8 Interrupt Mask Register Register Name: IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - RES 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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AT32UC3C 19.8.9 Interrupt Status Register Register Name: ISR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - RES • RES: Refresh Error Status This bit is set when a refresh error is detected. This bit is cleared when the register is read.
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AT32UC3C 19.8.
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AT32UC3C 19.8.11 Version Register Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION 3 2 VERSION • Variant: Variant Number Reserved. No functionality associated. • Version: Version Number Version number of the module.No functionality associated.
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AT32UC3C 20. Peripheral DMA Controller (PDCA) Rev: 1.2.3.1 20.1 Features • • • • • • 20.
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AT32UC3C 20.3 Block Diagram Figure 20-1. PDCA Block Diagram Peripheral 0 Memory HSB to PB Bridge HSB Peripheral Bus HSB High Speed Bus Matrix HSB Interrupt Controller IRQ Peripheral 2 ... Peripheral DMA Controller (PDCA) Peripheral 1 Peripheral (n-1) Handshake Interfaces 20.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 20.4.
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AT32UC3C 20.4.4 20.5 20.5.1 Peripheral Events The PDCA peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. Functional Description Basic Operation The PDCA consists of multiple independent PDCA channels, each capable of handling DMA requests in parallel. Each PDCA channels contains a set of configuration registers which must be configured to start a DMA transfer.
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AT32UC3C If TCR is zero when writing to TCRR, the TCR and MAR are automatically updated with the value written in TCRR and MARR. 20.5.5 Ring Buffer When Ring Buffer mode is enabled the TCRR and MARR registers will not be cleared when TCR and MAR registers reload. This allows the PDCA to read or write to the same memory region over and over again until the transfer is actively stopped by the user. Ring Buffer mode is enabled by writing a one to the Ring Buffer bit in the Mode Register (MR.RING). 20.5.
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AT32UC3C 20.5.10 Priority If more than one PDCA channel is requesting transfer at a given time, the PDCA channels are prioritized by their channel number. Channels with lower numbers have priority over channels with higher numbers, giving channel zero the highest priority. 20.5.11 Error Handling If the Memory Address Register (MAR) is set to point to an invalid location in memory, an error will occur when the PDCA tries to perform a transfer.
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AT32UC3C The registers can also be manually reset by writing a one to the Channel Reset bit in the PCONTROL register (PCONTROL.CH0/1RES). The Performance Channel Read/Write Latency registers (PRLAT0/1 and PWLAT0/1) are saturating when their maximum count value is reached. The PRLAT0/1 and PWLAT0/1 registers can only be reset by writing a one to the corresponding reset bit in PCONTROL (PCONTROL.CH0/1RES).
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AT32UC3C 20.7 20.7.1 User Interface Memory Map Overview Table 20-1. PDCA Register Memory Map Address Range Contents 0x000 - 0x03F DMA channel 0 configuration registers 0x040 - 0x07F DMA channel 1 configuration registers ... ... (0x000 - 0x03F)+m*0x040 DMA channel m configuration registers 0x800-0x830 Performance Monitor registers 0x834 Version register The channels are mapped as shown in Table 20-1.
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AT32UC3C 20.7.3 Performance Monitor Memory Map Table 20-3.
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AT32UC3C 20.7.5 Name: Memory Address Register MAR Access Type: Read/Write Offset: 0x000 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 MADDR[31:24] 23 22 21 20 19 MADDR[23:16] 15 14 13 12 MADDR[15:8] 7 6 5 4 MADDR[7:0] • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the PDCA.
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AT32UC3C 20.7.6 Name: Peripheral Select Register PSR Access Type: Read/Write Offset: 0x004 + n*0x040 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PID • PID: Peripheral Identifier The Peripheral Identifier selects which peripheral should be connected to the DMA channel.
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AT32UC3C 20.7.7 Name: Transfer Counter Register TCR Access Type: Read/Write Offset: 0x008 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TCV[15:8] 7 6 5 4 TCV[7:0] • TCV: Transfer Counter Value Number of data items to be transferred by the PDCA. TCV must be programmed with the total number of transfers to be made.
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AT32UC3C 20.7.8 Name: Memory Address Reload Register MARR Access Type: Read/Write Offset: 0x00C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MARV[31:24] 23 22 21 20 MARV[23:16] 15 14 13 12 MARV[15:8] 7 6 5 4 MARV[7:0] • MARV: Memory Address Reload Value Reload Value for the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a nonzero value.
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AT32UC3C 20.7.9 Name: Transfer Counter Reload Register TCRR Access Type: Read/Write Offset: 0x010 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TCRV[15:8] 7 6 5 4 TCRV[7:0] • TCRV: Transfer Counter Reload Value Reload value for the TCR register. When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value.
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AT32UC3C 20.7.10 Name: Control Register CR Access Type: Write-only Offset: 0x014 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - ECLR 7 6 5 4 3 2 1 0 - - - - - - TDIS TEN • ECLR: Transfer Error Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Error bit in the Status Register (SR.TERR).
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AT32UC3C 20.7.11 Name: Mode Register MR Access Type: Read/Write Offset: 0x018 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - RING ETRIG SIZE • RING: Ring Buffer 0:The Ring buffer functionality is disabled. 1:The Ring buffer functionality is enabled.
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AT32UC3C 20.7.12 Name: Status Register SR Access Type: Read-only Offset: 0x01C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - TEN • TEN: Transfer Enabled This bit is cleared when the TDIS bit in CR is written to one. This bit is set when the TEN bit in CR is written to one.
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AT32UC3C 20.7.13 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x020 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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AT32UC3C 20.7.14 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x024 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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AT32UC3C 20.7.15 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x028 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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AT32UC3C 20.7.16 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x02C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ • TERR: Transfer Error This bit is cleared when no transfer errors have occurred since the last write to CR.ECLR.
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AT32UC3C 20.7.
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AT32UC3C 20.7.
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AT32UC3C 20.7.
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AT32UC3C 20.7.20 Name: Performance Channel 0 Read Max Latency PRLAT0 Access Type: Read/Write Offset: 0x80C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating.
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AT32UC3C 20.7.
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AT32UC3C 20.7.
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AT32UC3C 20.7.23 Name: Performance Channel 0 Write Max Latency PWLAT0 Access Type: Read/Write Offset: 0x818 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating.
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AT32UC3C 20.7.
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AT32UC3C 20.7.
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AT32UC3C 20.7.26 Name: Performance Channel 1 Read Max Latency PRLAT1 Access Type: Read/Write Offset: 0x824 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating.
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AT32UC3C 20.7.
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AT32UC3C 20.7.
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AT32UC3C 20.7.29 Name: Performance Channel 1 Write Max Latency PWLAT1 Access Type: Read/Write Offset: 0x830 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating.
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AT32UC3C 20.7.30 Name: PDCA Version Register VERSION Access Type: Read-only Offset: 0x834 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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AT32UC3C 20.8 Module Configuration The specific configuration for the PDCA instance is listed in the following tables. Table 20-6. PDCA Configuration Features PDCA Number of channels 16 Number of performance monitors 1 Table 20-7. Module Clock Name Module name Clock name Description CLK_PDCA_HSB HSB clock CLK_PDCA_PB Peripheral Bus clock from the PBC clock domain PDCA Table 20-8.
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AT32UC3C Table 20-9.
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AT32UC3C 21. Memory DMA Controller (MDMA) Rev 1.0.1.1 21.1 Features • • • • • • • • • 21.
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AT32UC3C 21.3.4 21.4 21.4.1 Debug Operation When an external debugger forces the CPU into debug mode, the MDMA continues normal operation. If the MDMA is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.
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AT32UC3C In Round-Robin Mode, other channels with transfers pending will preempt the current channel in a round-robin fashion. This eliminates the possibility of starvation. 21.4.4 Aborting Transfers Transfers on any channel can be gracefully aborted by writing a one to the corresponding Channel Disable bit in the Control Register (CR.CHxDIS). Note that in order to successfully write to CHxDIS, the same write operation must also write a one to the corresponding Channel Enable bit (CR.CHxEN).
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AT32UC3C 21.6 Descriptor Mode The Descriptor Mode (DM) performs a series of single transfers. Data describing the transfers to be performed are written to memory by software, forming a queue of descriptors, each descriptor describing a transfer to be performed. 21.6.1 Setting Up and Using the Descriptors Before being able to use the Descriptor Mode, the channel’s Descriptor Start Address (DSARx) register must be initialized to point to the first descriptor in the queue.
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AT32UC3C Figure 21-2. Descriptors in Memory Descriptor 1 Descriptor n Dn RAR Dn WAR Dn CCR UNUSED DSAR Wrapping Addresses Descriptor 0 Growing Memory Addresses 21.6.3 D0 RAR D0 WAR D0 CCR UNUSED D1 RAR D1 WAR D1 CCR UNUSED Last bit set Adding Descriptors to a List In order to add descriptors to a list, the following actions must be performed: 1. Check if there are free entries in the list for the desired channel. Any entry with the V bit cleared is free.
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AT32UC3C 21.7 User interface Table 21-1.
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AT32UC3C 21.7.1 Name: Control Register CR Access Type : Read/Write Offset: 0x00 Reset Value: 0x000000000 31 30 29 28 27 26 25 24 - - - - - - - ARB 23 22 21 20 19 18 17 16 - - - - CH3DIS CH2DIS CH1DIS CH0DIS 15 14 13 12 11 10 9 8 - - - - CH3M CH2M CH1M CH0M 7 6 5 4 3 2 1 0 - - - - CH3EN CH2EN CH1EN CH0EN • ARB: Arbitration Mode 0: The MDMA is in Fixed Priority Mode. 1: The MDMA is in Round-Robin Mode.
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AT32UC3C 21.7.2 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x04 Reset Value: 0x000000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - BERR3 BERR2 BERR1 BERR0 7 6 5 4 3 2 1 0 - - - - CH3C CH2C CH1C CH0C Writing a zero to a bit in this register has no effect.
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AT32UC3C 21.7.3 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x08 Reset Value: 0x000000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - BERR3 BERR2 BERR1 BERR0 7 6 5 4 3 2 1 0 - - - - CH3C CH2C CH1C CH0C Writing a zero to a bit in this register has no effect.
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AT32UC3C 21.7.4 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x0C Reset Value: 0x000000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - BERR3 BERR2 BERR1 BERR0 7 6 5 4 3 2 1 0 - - - - CH3C CH2C CH1C CH0C 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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AT32UC3C 21.7.5 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x10 Reset Value: 0x000000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - BERR3 BERR2 BERR1 BERR0 7 6 5 4 3 2 1 0 - - - - CH3C CH2C CH1C CH0C • BERRx: Channel Bus Error This bit is cleared when the corresponding bit in ICR is written to one.
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AT32UC3C 21.7.6 Name: Interrupt Clear Register ICR Access Type: Write-only Offset: 0x14 Reset Value: 0x000000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - BERR3 BERR2 BERR1 BERR0 7 6 5 4 3 2 1 0 - - - - CH3C CH2C CH1C CH0C Writing a zero to a bit in this register has no effect.
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AT32UC3C 21.7.7 Name: Parameter Register PR Access Type: Read-only Offset: 0x18 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - - - - CH3I CH2I CH1I CH0I BURST • BURST: Maximum Burst Size The maximum burst size that can be used is a function of the FIFO size, which can be different in different devices.
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AT32UC3C 21.7.8 Name: Version Register VR Access Type: Read-only Offset: 0x1C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VERSION: Version Number Version number of the module. No functionality associated.
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AT32UC3C 21.7.9 Name: Descriptor Start Address Register x DSAR0, DSAR1, DSAR2, DSAR3 Access Type: Read/Write Offset: 0x20, 0x24, 0x28, 0x2C Reset Value: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DSAR[31:24] 23 22 21 20 DSAR[23:16] 15 14 13 12 DSAR[15:8] 7 6 5 4 DSAR[7:0] • DSAR: Descriptor Start Address Register The address of the first descriptor in the chain. When the hardware has read a descriptor with the CCRx.
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AT32UC3C 21.7.10 Name: Current Descriptor Address Register x CDAR0, CDAR1, CDAR2, CDAR3 Access Type: Read/Write Offset: 0x40, 0x50, 0x60, 0x70 Reset Value: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDAR[31:24] 23 22 21 20 CDAR[23:16] 15 14 13 12 CDAR[15:8] 7 6 5 4 CDAR[7:0] • CDAR: Current Descriptor Address Register The memory address pointing to the currently active descriptor.
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AT32UC3C 21.7.11 Name: Read Address Register x RAR0, RAR1, RAR2, RAR3 Access Type: Read/Write Offset: 0x44, 0x54, 0x64, 0x74 Reset Value: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RAR[31:24] 23 22 21 20 RAR[23:16] 15 14 13 12 RAR[15:8] 7 6 5 4 RAR[7:0] • RAR: Read Address Register The memory address that the next read access will be done from. Must be aligned according to the transfer size.
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AT32UC3C 21.7.12 Name: Write Address Register x WAR0, WAR1, WAR2, WAR3 Access Type: Read/Write Offset: 0x48, 0x58, 0x68, 0x78 Reset Value: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 WAR[31:24] 23 22 21 20 WAR[23:16] 15 14 13 12 WAR[15:8] 7 6 5 4 WAR[7:0] • WAR: Write Address Register The memory address that the next write access will be done to. Must be aligned according to the transfer size.
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AT32UC3C 21.7.13 Name: Channel Control Register x CCR0, CCR1, CCR2, CCR3 Access Type: Read/Write Offset: 0x4C, 0x5C, 0x6C, 0x7C Reset Value: 0x000000000 31 30 29 28 27 26 - - - - - - 23 22 21 20 19 18 - L V TCIE 15 14 13 12 25 24 BSWP 17 BURST 16 SIZE 11 10 9 8 3 2 1 0 TCNT[15:8] 7 6 5 4 TCNT[7:0] • BSWP: Byte Swap Allows swapping of the transferred bytes. See Section 21.4.2 for additional details.
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AT32UC3C • BURST: Transfer Burst Size Indicates the size of the burst used for data transfer. The MDMA will always try to use this burst size to perform transfers, but may be forced to use smaller sizes since the transfer count may not be perfectly divisible by the transfer data size: Table 21-4. Transfer Burst Size BURST Transfer Burst Size 0 Single transfer 1 4-beat burst 2 8-beat burst 3 16-beat burst • SIZE: Transfer Data Size Indicates the size of data to transfer: Table 21-5.
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AT32UC3C 21.8 Module Configuration The specific configuration for each MDMA instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 21-6. Module Configuration Feature MDMA Channels 1 Maximum burst size Single Transfer Table 21-7.
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AT32UC3C 22. Secure Access Unit (SAU) Rev: 1.1.1.3 22.
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AT32UC3C 22.3 Block Diagram Figure 22-1 presents the SAU integrated in an example system with a CPU, some memories, some peripherals, and a bus system. The SAU is connected to both the Peripheral Bus (PB) and the High Speed Bus (HSB). Configuration of the SAU is done via the PB, while memory accesses are done via the HSB. The SAU receives an access on its HSB slave interface, remaps it, checks that the channel is unlocked, and if so, initiates a transfer on its HSB master interface to the remapped address.
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AT32UC3C 22.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 22.4.1 Power Management If the CPU enters a sleep mode that disables clocks used by the SAU, the SAU will stop functioning and resume operation after the system wakes up from sleep mode. 22.4.2 Clocks The SAU has two bus clocks connected: One High Speed Bus clock (CLK_SAU_HSB) and one Peripheral Bus clock (CLK_SAU_PB).
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AT32UC3C 22.5.2.1 22.5.3 Protecting SAU configuration registers In order to prevent the SAU configuration registers to be changed by malicious or runaway code, they should be protected by the MPU as soon as they have been configured. Maximum security is provided in the system if program memory does not contain any code to unprotect the configuration registers in the MPU. This guarantees that runaway code can not accidentally unprotect and thereafter change the SAU configuration registers.
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AT32UC3C 22.5.4.1 Operation example Figure 22-2 shows a typical memory map, consisting of some memories, some simple peripherals, and a SAU with multiple channels and an Unlock Register (UR). Imagine that the MPU has been set up to disallow all accesses from the CPU to the grey modules. Thus the CPU has no way of accessing for example the Transmit Holding register in the UART, present on address X on the bus. Note that the SAU RTRs are not protected by the MPU, thus the RTRs can be accessed.
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AT32UC3C • Unlock Register Error Status (URES) is set if an attempt was made to unlock a channel by writing to the Unlock Register while one or more error bits in SR were set (see Section 22.5.6). The unlock operation was aborted. • Unlock Register Key Error (URKEY) is set if the Unlock Register was attempted written with an invalid key. • Unlock Register Read (URREAD) is set if the Unlock Register was attempted read. • Channel Access Unsuccessful (CAU) is set if the channel access was unsuccessful.
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AT32UC3C 22.6 User Interface The following addresses are used by SAU channel configuration registers. All offsets are relative to the SAU’s PB base address. Table 22-1.
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AT32UC3C 22.6.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - BERRDIS BERREN SDIS SEN DIS EN • BERRDIS: Bus Error Response Disable Writing a zero to this bit has no effect. Writing a one to this bit disables Bus Error Response from the SAU.
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AT32UC3C 22.6.2 Name: Configuration Register CONFIG Access Type: Write-only Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - OPEN 15 14 13 12 11 10 9 8 3 2 1 0 UCYC 7 6 5 4 UKEY • OPEN: Open Mode Enable Writing a zero to this bit disables open mode. Writing a one to this bit enables open mode.
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AT32UC3C 22.6.3 Name: Channel Enable Register High CERH Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 - 23 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CERH[30:24] 22 21 20 CERH[23:16] 15 14 13 12 CERH[15:8] 7 6 5 4 CERH[7:0] • CERH[n]: Channel Enable Register High 0: Channel (n+32) is not enabled. 1: Channel (n+32) is enabled.
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AT32UC3C 22.6.4 Name: Channel Enable Register Low CERL Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CERL[31:24] 23 22 21 20 CERL[23:16] 15 14 13 12 CERL[15:8] 7 6 5 4 CERL[7:0] • CERL[n]: Channel Enable Register Low 0: Channel n is not enabled. 1: Channel n is enabled.
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AT32UC3C 22.6.5 Name: Status Register SR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000400 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - IDLE SEN EN 7 6 5 4 3 2 1 0 RTRADR MBERROR URES URKEY URREAD CAU CAS EXP • IDLE • • • • • • • This bit is cleared when a read or write operation to the SAU channel is started.
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AT32UC3C • CAU: Channel Access Unsuccessful This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if channel access was unsuccessful, i.e. an access was attempted to a locked or disabled channel. • CAS: Channel Access Successful This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if channel access successful, i.e. one access was made after the channel was unlocked.
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AT32UC3C 22.6.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RTRADR MBERROR URES URKEY URREAD CAU CAS EXP Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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AT32UC3C 22.6.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RTRADR MBERROR URES URKEY URREAD CAU CAS EXP Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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AT32UC3C 22.6.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RTRADR MBERROR URES URKEY URREAD CAU CAS EXP 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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AT32UC3C 22.6.9 Name: Interrupt Clear Register ICR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RTRADR MBERROR URES URKEY URREAD CAU CAS EXP Writing a zero to a bit in this register has no effect.
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AT32UC3C 22.6.10 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x24 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CHANNELS • CHANNELS: Number of channels implemented.
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AT32UC3C 22.6.11 Name: Version Register VERSION Access Type: Write-only Offset: 0x28 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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AT32UC3C 22.6.
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AT32UC3C 22.6.13 Name: Unlock Register UR Access Type : Write-only Offset: 0xFC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 KEY 7 6 - - 5 4 CHANNEL • KEY: Unlock Key The correct key must be written in order to unlock a channel. The key value written must correspond to the key value defined in CONFIG.UKEY.
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AT32UC3C 22.7 Module configuration The specific configuration for each SAU instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 22-3. Module configuration Feature SAU SAU Channels 16 Table 22-4. Module name Module clock name Clock name Description CLK_SAU_HSB HSB clock CLK_SAU_PB Peripheral Bus clock from the PBB clock domain SAU Table 22-5.
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AT32UC3C 23. General-Purpose Input/Output Controller (GPIO) Rev: 2.1.2.5 23.1 Features • • • • • • • • 23.
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AT32UC3C 23.4 I/O Lines Description Pin Name Description Type GPIOn GPIO pin n Digital 23.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 23.5.1 Power Management If the CPU enters a sleep mode that disables clocks used by the GPIO, the GPIO will stop functioning and resume operation after the system wakes up from sleep mode.
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AT32UC3C 23.6 Functional Description The GPIO controls the I/O pins of the microcontroller. The control logic associated with each pin is shown in the figure below. Figure 23-2. Overview of the GPIO PDER* PUER* ODER 1 0 Periph. Func. A Output Pullup, Pulldown and buskeeper 0 Periph.Func. B Periph. Func. C 1 ....
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AT32UC3C 23.6.1 Basic Operation 23.6.1.1 Module Configuration The GPIO user interface registers are organized into ports and each port controls 32 different GPIO pins. Most of the registers supports bit wise access operations such as set, clear and toggle in addition to the standard word access. For details regarding interface registers, refer to Section 23.7. 23.6.1.2 Available Features The GPIO features implemented are device dependent, and not all functions are implemented on all pins.
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AT32UC3C 23.6.2 23.6.2.1 Advanced Operation Peripheral I/O Pin Control When a GPIO pin is assigned to a peripheral function, i.e. the corresponding bit in GPER is zero, output and output enable is controlled by the selected peripheral pin. In addition the peripheral may control some or all of the other GPIO pin functions listed in Table 23-1, if the peripheral supports those features. All pin features not controlled by the selected peripheral is controlled by the GPIO.
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AT32UC3C 23.6.2.4 Pin Output Driver Control The GPIO has registers for controlling output drive properties of each pin, such as output driving capability. The driving capability is controlled by the Output Driving Capability Registers (ODCRn). 23.6.2.5 Interrupts The GPIO can be configured to generate an interrupt when it detects a change on a GPIO pin. Interrupts on a pin are enabled by writing a one to the corresponding bit in the Interrupt Enable Register (IER).
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AT32UC3C Figure 23-4. Interrupt Timing with Glitch Filter Disabled CLK_GPIO Pin Level IFR Figure 23-5 shows the timing for rising edge (or pin-change) interrupts when the glitch filter is enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges. In the example, the first pulse is rejected while the second pulse is accepted and causes an interrupt request. Figure 23-5. Interrupt Timing with Glitch Filter Enabled CLK_GPIO Pin Level IFR 23.6.2.
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AT32UC3C 23.7 User Interface The GPIO controller manages all the GPIO pins on the 32-bit AVR microcontroller. The pins are managed as 32-bit ports that are configurable through a Peripheral Bus (PB) interface. Each port has a set of configuration registers. The overall memory map of the GPIO is shown below. The number of pins and hence the number of ports is product specific. Figure 23-6. Port Configuration Registers 0x0000 Port 0 Configuration Registers 0x0200 Port 1 Configuration Registers 0x0400 ….
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AT32UC3C ten to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g. IFR), not all access methods are permitted. Note that for ports with less than 32 bits, the corresponding control registers will have unused bits. This is also the case for features that are not implemented for a specific pin. Writing to an unused bit will have no effect. Reading unused bits will always return 0. 23.7.
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AT32UC3C Table 23-2. GPIO Register Memory Map Offset Register Function Register Name Access 0x02C Peripheral Mux Register 1 Toggle PMR1T Write-only Reset - (1) Config.
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AT32UC3C Table 23-2. GPIO Register Memory Map Offset Register Function Register Name Access Reset Config.
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AT32UC3C 23.7.4 Name: GPIO Enable Register GPER Access: Read/Write, Set, Clear, Toggle Offset: 0x000, 0x004, 0x008, 0x00C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: GPIO Enable 0: A peripheral function controls the corresponding pin.
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AT32UC3C 23.7.
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AT32UC3C 23.7.
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AT32UC3C 23.7.
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AT32UC3C 23.7.8 Name: Output Driver Enable Register ODER Access: Read/Write, Set, Clear, Toggle Offset: 0x040, 0x044, 0x048, 0x04C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Driver Enable 0: The output driver is disabled for the corresponding pin.
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AT32UC3C 23.7.9 Name: Output Value Register OVR Access: Read/Write, Set, Clear, Toggle Offset: 0x050, 0x054, 0x058, 0x05C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Value 0: The value to be driven on the GPIO pin is 0.
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AT32UC3C 23.7.10 Name: Pin Value Register PVR Access: Read-only Offset: 0x060, 0x064, 0x068, 0x06C Reset Value: Depending on pin states 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Pin Value 0: The GPIO pin is at level zero. 1: The GPIO pin is at level one.
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AT32UC3C 23.7.
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AT32UC3C 23.7.
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AT32UC3C 23.7.13 Name: Interrupt Enable Register IER Access: Read/Write, Set, Clear, Toggle Offset: 0x090, 0x094, 0x098, 0x09C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Enable 0: Interrupt is disabled for the corresponding pin.
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AT32UC3C 23.7.
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AT32UC3C 23.7.
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AT32UC3C 23.7.16 Name: Glitch Filter Enable Register GFER Access: Read/Write, Set, Clear, Toggle Offset: 0x0C0, 0x0C4, 0x0C8, 0x0CC Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Glitch Filter Enable 0: Glitch filter is disabled for the corresponding pin.
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AT32UC3C 23.7.17 Name: Interrupt Flag Register IFR Access: Read, Clear Offset: 0x0D0, 0x0D8 Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Flag 0: No interrupt condition has been detected on the corresponding pin.
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AT32UC3C 23.7.
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AT32UC3C 23.7.
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AT32UC3C 23.7.20 Name: Lock Register LOCK Access: Read/Write, Set, Clear, Toggle Offset: 0x1A0, 0x1A4, 0x1A8, 0x1AC Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Lock State 0: Pin is unlocked.
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AT32UC3C 23.7.21 Name: Unlock Register UNLOCK Access: Write-only Offset: 0x1E0 Reset Value: - 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 - - - - - - 7 6 5 4 3 2 8 OFFSET 1 0 OFFSET • OFFSET: Register Offset This field must be written with the offset value of the LOCK, LOCKC or LOCKT register to unlock. This offset must also include the port offset for the register to unlock.
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AT32UC3C 23.7.22 Name: Access Status Register ASR Access: Read/Write Offset: 0x1E4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - AE • AE: Access Error This bit is set when a write to a locked register occurs. This bit can be written to 0 by software.
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AT32UC3C 23.7.23 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x1F8 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PARAMETER 23 22 21 20 PARAMETER 15 14 13 12 PARAMETER 7 6 5 4 PARAMETER • PARAMETER: 0: The corresponding pin is not implemented in this GPIO port. 1: The corresponding pin is implemented in this GPIO port. There is one PARAMETER register per GPIO port.
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AT32UC3C 23.7.24 Name: Version Register VERSION Access Type: Read-only Offset: 0x1FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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AT32UC3C 23.8 Module Configuration The specific configuration for each GPIO instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 23-3. Module Configuration Feature GPIO Number of GPIO ports 4 Number of peripheral functions 4 Table 23-4.
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AT32UC3C Table 23-6.
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AT32UC3C 24. Ethernet MAC (MACB) Rev: 1.1.2.6 24.1 Features • • • • • • • • • • • • • • • • • • • • • • 24.2 Compatible with IEEE Standard 802.
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AT32UC3C 24.3 Block Diagram Figure 24-1. MACB Block Diagram Address Checker Peripheral Bus Slave Register Interface Statistics Registers MDIO Control Registers DMA Interface RX FIFO TX FIFO Ethernet Receive High Speed Bus Master 24.4 MII/RMII Ethernet Transmit Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 24.4.1 I/O Lines The pins used for interfacing the MACB may be multiplexed with the I/O Controller lines.
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AT32UC3C ager. It is recommended to disable the MACB before disabling the clocks, to avoid freezing the MACB in an undefined state. The synchronization module in the MACB requires that the bus clock (CLK_MACB_HSB) runs on at least the speed of the macb_tx/RX_CLK, which is 25MHz in 100Mbps, and 2.5MHZ in 10Mbps in MII mode and 50MHz in 100Mbps, and 5MHZ in 10Mbps in RMII mode. 24.4.4 Interrupt The MACB interrupt request line is connected to the interrupt controller.
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AT32UC3C 3. Transmit data DMA read 4. Receive data DMA write 5. Transmit buffer manager read 6. Transmit buffer manager write 24.5.2 FIFO FIFO depths are 124 bytes. Data is typically transferred in and out of the FIFOs in bursts of four words. In reception, a bus request is asserted when the FIFO contains four words and has space for three more.
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AT32UC3C Table 24-1. Receive Buffer Descriptor Entry (Continued) Bit Function 28 External address match 27 Reserved for future use 26 Specific address register 1 match 25 Specific address register 2 match 24 Specific address register 3 match 23 Specific address register 4 match 22 Type ID match 21 VLAN tag detected (i.e., type id of 0x8100) 20 Priority tag detected (i.e.
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AT32UC3C The System Bus specification requires that bursts should not cross 1K boundaries. As receive buffer manager writes are bursts of two words, to ensure that this does not occur, it is best to write the pointer register with the least three significant bits set to zero. As receive buffers are used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate used. If a receive error is detected the receive buffer currently being written is recovered.
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AT32UC3C whether or not it is to be transmitted with CRC and whether the buffer is the last buffer in the frame. After transmission, the control bits are written back to the second word of the first buffer along with the “used” bit and other status information. Before a transmission, bit 31 is the “used” bit which must be zero when the control word is read. It is written to one when a frame has been transmitted. Bits 27, 28 and 29 indicate various transmit error conditions.
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AT32UC3C Table 24-2. Transmit Buffer Descriptor Entry (Continued) Bit Function 31 Used. Needs to be zero for the MACB to read data from the transmit buffer. The MACB sets this to one for the first buffer of a frame once it has been successfully transmitted. Software has to clear this bit before the buffer can be used again. Note: This bit is only set for the first buffer in a frame unlike receive where all buffers have the Used bit set once used. 30 Wrap.
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AT32UC3C 64 1s, whenever it sees an incoming frame to force a collision. This provides a way of implementing flow control in half-duplex mode. 24.5.6 Pause Frame Support The start of an 802.3 pause frame is as follows: Table 24-3. Start of an 802.3 Pause Frame Destination Address Source Address Type (Mac Control Frame) Pause Opcode Pause Time 0x0180C2000001 6 bytes 0x8808 0x0001 2 bytes The network configuration register contains a receive pause enable bit (13).
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AT32UC3C • fill of 00 to take the frame to minimum frame length • valid FCS The pause quantum used in the generated frame depends on the trigger source for the frame as follows: 1. If bit 11 is written with a one, the pause quantum comes from the transmit pause quantum register. The Transmit Pause Quantum register resets to a value of 0xFFFF giving a maximum pause quantum as a default. 2. If bit 12 is written with a one, the pause quantum is zero. 3.
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AT32UC3C register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes. The addresses stored can be specific, group, local or universal. The destination address of received frames is compared against the data stored in the specific address registers once they have been activated. The addresses are deactivated at reset or when their corresponding specific address register bottom is written.
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AT32UC3C The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. The destination address is reduced to a 6-bit index into the 64-bit hash register using the following hash function. The hash function is an exclusive or of every sixth bit of the destination address.
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AT32UC3C 24.5.14 VLAN Support An Ethernet encoded 802.1Q VLAN tag looks like this: Table 24-4. 802.1Q VLAN Tag TPID (Tag Protocol Identifier) 16 bits TCI (Tag Control Information) 16 bits 0x8100 First 3 bits priority, then CFI bit, last 12 bits VID The VLAN tag is inserted at the 13th byte of the frame, adding an extra four bytes to the frame. If the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame.
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AT32UC3C • the frame has a broadcast destination address (bytes 1 to 6) • the frame has a typeID field of 0x0806 (bytes 13 and 14) • the frame has an ARP operation field of 0x0001 (bytes 21 and 22) • the least significant 16 bits of the frame ARP target protocol (bytes 41 and 42) match the value written in WOL.IP. The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame.
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AT32UC3C The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in Table 24-5. Table 24-5.
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AT32UC3C 24.6 24.6.1 Programming Interface Configuration Initialization of the MACB configuration (e.g. frequency ratios) must be done while the transmit and receive circuits are disabled. Network control register and network configuration register are described below. 24.6.2 Receive Buffer List Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed in another data structure that also resides in main memory.
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AT32UC3C 24.6.3 Transmit Buffer List Transmit data is read from the system memory These buffers are listed in another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of descriptor entries (as defined in Table 24-2 on page 494) that points to this data structure. To create this list of buffers: 1. Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. Up to 128 buffers per frame are allowed. 2.
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AT32UC3C 24.6.7 Receiving Frames When a frame is received and the receive circuits are enabled, the MACB checks the address and, in the following cases, the frame is written to system memory: • if it matches one of the four specific address registers. • if it matches the hash address function. • if it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed. • if the MACB is configured to copy all frames. • if the EAM is asserted before four words have been loaded into the receive FIFO.
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AT32UC3C 24.7 User Interface Table 24-6.
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AT32UC3C Table 24-6. 1.
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AT32UC3C 24.7.
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AT32UC3C • RE: Receive Enable 0: Frame reception stops immediately and the receive FIFO is cleared. The receive queue pointer register is unaffected. 1: Enables the MACB to receive data. • LLB: Local Loopback 0: Local loopback is disabled. 1: Local loopback is enabled. It connects TXD to RXD, TX_EN to RX_DV, forces full duplex and drives RX_CLK and TX_CLK with CLK_MACB_PB divided by 4. RX_CLK and TX_CLK may glitch as the MACB is switched into and out of internal loop back.
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AT32UC3C 24.7.2 Name: Network Configuration Register NCFGR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00008000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - IRXFCS EFRHD DRFCS RLCE 15 14 13 12 11 10 9 8 PAE RTY EAE FS RBOF CLK 7 6 5 4 3 2 1 0 UNI MTI NBC CAF JFRAME BR FD SPD • IRXFCS: Ignore RX FCS 0: Normal operation.
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AT32UC3C • RTY: Retry Test 0: Normal operation. 1: The back off between collisions is always one slot time. It helps testing the too many retries condition. Also used in the pause frame tests to reduce the pause counters decrement time from 512 bit times, to every RX_CLK cycle. • CLK: PB Clock Divider Determines by what number system clock is divided to generate Divided PB Clock (DPC). For conformance with 802.3, DPC must not exceed 2.5MHz (DPC is only active during MDIO read and write operations).
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AT32UC3C 24.7.3 Name: Network Status Register NSR Access Type: Read-only Offset: 0x08 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - IDLE MDIO - • IDLE: IDLE Status 0: PHY management logic is idle (i.e., has completed). 1: PHY management logic is running.
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AT32UC3C 24.7.4 Name: Transmit Status Register TSR Access Type: Read/Write Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - UND COMP BEX TGO RLE COL UBR This register, when read, returns details of the status of a transmit. Once read, individual bits may be cleared by writing a one to them.
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AT32UC3C 1: Retry limit is exceeded. • COL: Collision Occurred This bit is set by the assertion of collision. Write a one to clear this bit. 0: No collision detected. 1: Collision detected. • UBR: Used Bit Read This bit is set when a transmit buffer descriptor is read with its used bit set. Write a one to clear this bit. 0: Used bit is not set. 1: Used bit set.
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AT32UC3C 24.7.5 Name: Receive Buffer Queue Pointer Register RBQP Access Type: Read/Write Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 - - ADDR[29:22] 23 22 21 20 ADDR[21:14] 15 14 13 12 ADDR[13:6] 7 6 5 4 ADDR[5:0] This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list.
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AT32UC3C 24.7.6 Name: Transmit Buffer Queue Pointer Register TBQP Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 - - ADDR[29:22] 23 22 21 20 ADDR[21:14] 15 14 13 12 ADDR[13:6] 7 6 5 4 ADDR[5:0] This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list.
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AT32UC3C 24.7.7 Name: Receive Status Register RSR Access Type: Read/Write Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - OVR REC BNA This register, when read, returns details of the status of a receive. Once read, individual bits may be cleared by writing a one to them.
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AT32UC3C 24.7.8 Name: Interrupt Status Register ISR Access Type: Read/Write Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - PTZ PFR HRESP ROVR - - 7 6 5 4 3 2 1 0 TCOMP TXERR RLE TUND TXUBR RXUBR RCOMP MFD • PTZ: Pause Time Zero This bit is set when the pause time register (PTR) decrements to zero. This bit is cleared after read. 0: PTR > 0.
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AT32UC3C • • • • • • This bit is cleared after read. 0: No transmit error. 1: Transmit error detected. RLE: Retry Limit Exceeded This bit is cleared after read. 0: Retry limit is not exceeded. 1: Retry limit is exceeded. TUND: Ethernet Transmit Buffer Underrun This bit is set if the DMA did not fetch frame data to transmit in time or HRESP returned not OK. It is also set if a used bit is read mid-frame or when a new transmit queue pointer is written. This bit is cleared after read.
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AT32UC3C 24.7.9 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - PTZ PFR HRESP ROVR - - 7 6 5 4 3 2 1 0 TCOMP TXERR RLE TUND TXUBR RXUBR RCOMP MFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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AT32UC3C 24.7.10 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - PTZ PFR HRESP ROVR - - 7 6 5 4 3 2 1 0 TCOMP TXERR RLE TUND TXUBR RXUBR RCOMP MFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 522
AT32UC3C 24.7.11 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x30 Reset Value: 0x00003FFF 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - PTZ PFR HRESP ROVR - - 7 6 5 4 3 2 1 0 TCOMP TXERR RLE TUND TXUBR RXUBR RCOMP MFD 0: The corresponding interrupt is enabled. 1: The corresponding interrupt is disabled.
PAGE 523
AT32UC3C 24.7.12 Name: PHY Maintenance Register MAN Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 SOF 23 27 26 RW 22 21 PHYA 15 28 25 24 17 16 PHYA[4:1] 20 19 18 REGA 14 13 CODE 12 11 10 9 8 3 2 1 0 DATA[15:8] 7 6 5 4 DATA[7:0] • SOF: Start Of Frame Must be written to 01 for a valid frame. • RW: Read/Write 10: Read operation 01: Write operation. Any other value is an invalid PHY management frame • PHYA: PHY Address PHY address.
PAGE 524
AT32UC3C 24.7.13 Name: Pause Time Register PTR Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 PTIME[15:8] 7 6 5 4 PTIME[7:0] • PTIME: Pause Time Current value of the pause time register which is decremented every 512 bit times.
PAGE 525
AT32UC3C 24.7.14 Name: Pause Frames Received Register PFR Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 PFROK[15:8] 7 6 5 4 PFROK[7:0] • PFROK: Pauses Frames Received OK Number of good pause frames received. A good frame has a length of 64 to 1518 bytes (1536 if bit NCFGR.FS is set, 10240 if bit NCFGR.
PAGE 526
AT32UC3C 24.7.15 Name: Frames Transmitted OK Register FTO Access Type: Read/Write Offset: 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 FTOK[23:16] 15 14 13 12 FTOK[15:8] 7 6 5 4 FTOK[7:0] • FTOK: Frames Transmitted OK Number of frames successfully transmitted, i.e., no underrun and not too many retries.
PAGE 527
AT32UC3C 24.7.16 Name: Single Collision Frames Register SCF Access Type: Read/Write Offset: 0x44 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 SCF[15:8] 7 6 5 4 SCF[7:0] • SCF: Single Collision Frames Number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun.
PAGE 528
AT32UC3C 24.7.17 Name: Multicollision Frames Register MCF Access Type: Read/Write Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 MCF[15:8] 7 6 5 4 MCF[7:0] • MCF: Multicollision Frames Number of frames experiencing between 2 and 15 collisions prior to being successfully transmitted, i.e., no underrun and not too many retries.
PAGE 529
AT32UC3C 24.7.18 Name: Frames Received OK Register FRO Access Type: Read/Write Offset: 0x4C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 FROK[23:16] 15 14 13 12 FROK[15:8] 7 6 5 4 FROK[7:0] • FROK: Frames Received OK Number of frames successfully received, i.e., address recognized and successfully copied to memory. A good frame has a length of 64 to 1518 bytes (1536 if bit NCFGR.
PAGE 530
AT32UC3C 24.7.19 Name: Frames Check Sequence Errors Register FCSE Access Type: Read/Write Offset: 0x50 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 FCSE • FCSE: Frame Check Sequence Errors Number of frames which have an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit NCFGR.
PAGE 531
AT32UC3C 24.7.
PAGE 532
AT32UC3C 24.7.21 Name: Deferred Transmission Frames Register DTF Access Type: Read/Write Offset: 0x58 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 DTF[15:8] 7 6 5 4 DTF[7:0] • DTF: Deferred Transmission Frames Number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission.
PAGE 533
AT32UC3C 24.7.22 Name: Late Collisions Register LCOL Access Type: Read/Write Offset: 0x5C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 LCOL • LCOL: Late Collisions Number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision.
PAGE 534
AT32UC3C 24.7.23 Name: Excessive Collisions Register EXCOL Access Type: Read/Write Offset: 0x60 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 EXCOL • EXCOL: Excessive Collisions Number of frames that failed to be transmitted because they experienced 16 collisions.
PAGE 535
AT32UC3C 24.7.24 Name: Transmit Underrun Errors Register TUND Access Type: Read/Write Offset: 0x64 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TUND • TUND: Transmit Underruns Number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented.
PAGE 536
AT32UC3C 24.7.
PAGE 537
AT32UC3C 24.7.26 Name: Received Resource Errors Register RRE Access Type: Read/Write Offset: 0x6C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RRE[15:8] 7 6 5 4 RRE[7:0] • RRE: Received Resource Errors Number of frames that address matched but could not be copied to memory because no receive buffer was available.
PAGE 538
AT32UC3C 24.7.27 Name: Received Overrun Errors Register ROVR Access Type: Read/Write Offset: 0x70 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ROVR • ROVR: Received Overrun Errors Number of frames that are address recognized but were not copied to memory because of receive DMA overrun.
PAGE 539
AT32UC3C 24.7.28 Name: Received Symbol Errors Register RSE Access Type: Read/Write Offset: 0x74 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RSE • RSE: Received Symbol Errors Number of frames that had RX_ER asserted during reception.
PAGE 540
AT32UC3C 24.7.29 Name: Excessive Length Errors Register ELE Access Type: Read/Write Offset: 0x78 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 EXL • EXL: Excessive Length Errors Number of frames received exceeding 1518 bytes (1536 if bit NCFGR.FS is set, 10240 if bit NCFGR.
PAGE 541
AT32UC3C 24.7.30 Name: Receive Jabbers Register RJA Access Type: Read/Write Offset: 0x7C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RJB • RJB: Receive Jabbers Number of frames received exceeding 1518 bytes (1536 if bit NCFGR.FS is set, 10240 if bit NCFGR.
PAGE 542
AT32UC3C 24.7.31 Name: Undersize Frames Register USF Access Type: Read/Write Offset: 0x80 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 USF • USF: Undersize Frames Number of frames received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error.
PAGE 543
AT32UC3C 24.7.32 Name: SQE Test Errors Register STE Access Type: Read/Write Offset: 0x84 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 SQER • SQER: SQE Test Errors Number of frames where COL was not asserted within 96 bit times (interframe gap) of TX_EN being deasserted in half duplex mode.
PAGE 544
AT32UC3C 24.7.33 Name: Received Length Field Mismatch Register RLE Access Type: Read/Write Offset: 0x88 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RLFM • RLFM: Receive Length Field Mismatch Number of frames received that have a measured length shorter than extracted from its length field. Checking is enabled by bit NCFGR.RLCE.
PAGE 545
AT32UC3C 24.7.34 Name: Transmitted Pause Frames Register TPF Access Type: Read/Write Offset: 0x8C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TPF[15:8] 7 6 5 4 TPF[7:0] • TPF: Transmitted Pause Frames Number of pause frames transmitted.
PAGE 546
AT32UC3C 24.7.35 Name: Hash Register Bottom HRB Access Type: Read/Write Offset: 0x90 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR[31:24] 23 22 21 20 ADDR[23:16] 15 14 13 12 ADDR[15:8] 7 6 5 4 ADDR[7:0] • ADDR: Hash Address Low Low value of the hash address register. See ”Hash Addressing” on page 498.
PAGE 547
AT32UC3C 24.7.36 Name: Hash Register Top HRT Access Type: Read/Write Offset: 0x94 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR[31:24] 23 22 21 20 ADDR[23:16] 15 14 13 12 ADDR[15:8] 7 6 5 4 ADDR[7:0] • ADDR: Hash Address High High value of the hash address register. See ”Hash Addressing” on page 498.
PAGE 548
AT32UC3C 24.7.37 Name: Specific Address 1 Bottom Register SA1B Access Type: Read/Write Offset: 0x98 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR[31:24] 23 22 21 20 ADDR[23:16] 15 14 13 12 ADDR[15:8] 7 6 5 4 ADDR[7:0] • ADDR: Destination Address Low Low value of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
PAGE 549
AT32UC3C 24.7.38 Name: Specific Address 1 Top Register SA1T Access Type: Read/Write Offset: 0x9C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 ADDR[15:8] 7 6 5 4 ADDR[7:0] • ADDR: Destination Address High High value of the destination address (bits 32 to 47).
PAGE 550
AT32UC3C 24.7.39 Name: Specific Address 2 Bottom Register SA2B Access Type: Read/Write Offset: 0xA0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR[31:24] 23 22 21 20 ADDR[23:16] 15 14 13 12 ADDR[15:8] 7 6 5 4 ADDR[7:0] • ADDR: Destination Address Low Low value of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
PAGE 551
AT32UC3C 24.7.40 Name: Specific Address 2 Top Register SA2T Access Type: Read/Write Offset: 0xA4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 ADDR[15:8] 7 6 5 4 ADDR[7:0] • ADDR: Destination Address High High value of the destination address (bits 32 to 47).
PAGE 552
AT32UC3C 24.7.41 Name: Specific Address 3 Bottom Register SA3B Access Type: Read/Write Offset: 0xA8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR[31:24] 23 22 21 20 ADDR[23:16] 15 14 13 12 ADDR[15:8] 7 6 5 4 ADDR[7:0] • ADDR: Destination Address Low Low value of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
PAGE 553
AT32UC3C 24.7.42 Name: Specific Address 3 Top Register SA3T Access Type: Read/Write Offset: 0xAC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 ADDR[15:8] 7 6 5 4 ADDR[7:0] • ADDR: Destination Address High High value of the destination address (bits 32 to 47).
PAGE 554
AT32UC3C 24.7.43 Name: Specific Address 4 Bottom Register SA4B Access Type: Read/Write Offset: 0xB0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR[31:24] 23 22 21 20 ADDR[23:16] 15 14 13 12 ADDR[15:8] 7 6 5 4 ADDR[7:0] • ADDR: Destination Address Low Low value of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
PAGE 555
AT32UC3C 24.7.44 Name: Specific Address 4 Top Register SA4T Access Type: Read/Write Offset: 0xB4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 ADDR[15:8] 7 6 5 4 ADDR[7:0] • ADDR: Destination Address High High value of the destination address (bits 32 to 47).
PAGE 556
AT32UC3C 24.7.45 Name: Type ID Checking Register TID Access Type: Read/Write Offset: 0xB8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TID[15:8] 7 6 5 4 TID[7:0] • TID: Type ID Checking Comparison value for received frames (TypeID/Length field).
PAGE 557
AT32UC3C 24.7.46 Name: Transmit Pause Quantum Register TPQ Access Type: Read/Write Offset: 0xBC Reset Value: 0x0000FFFF 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TPQ[15:8] 7 6 5 4 TPQ[7:0] • TPQ: Transmit Pause Quantum Used in hardware generation of transmitted pause frames as value for pause quantum.
PAGE 558
AT32UC3C 24.7.47 Name: User Input/Output Register USRIO Access Type: Read/Write Offset: 0xC0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - WOL SPD BR HD LB 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - TPZ TP EAM RMII This register, when read, returns details of the status of a receive. Once read, individual bits 0 to 3 may be cleared by writing a one to them.
PAGE 559
AT32UC3C 24.7.48 Name: Wake-On-LAN Register WOL Access Type: Read/Write Offset: 0xC4 Reset Value: 0x0000FFFF 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - MTI SA1 ARP MAG 15 14 13 12 11 10 9 8 3 2 1 0 IP[15:8] 7 6 5 4 IP[7:0] • MTI: Multicast Hash Event Enable • • • • 0: Multicast hash events are disabled. 1:Multicast hash events assert WOL pin. SA1: Specific Address Register 1 Event Enable 0: SAR1 events are disabled.
PAGE 560
AT32UC3C 24.7.49 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 PR[15:8] 23 22 21 20 PR[7:0] 15 14 13 12 VERSION[15:8] 7 6 5 4 3 VERSION[7:0] • PR: Part Reference Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 561
AT32UC3C 24.8 Module Configuration The specific configuration for each MACB instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 24-7. Module name Module Clock Name Clock Name Description CLK_MACB_HSB HSB clock CLK_MACB_PB Peripheral Bus clock from the PBB clock domain MACB Table 24-8.
PAGE 562
AT32UC3C 25. Universal Synchronous Asynchronous Receiver Transmitter (USART) Rev: 6.0.2.1 25.1 Features • Programmable Baud Rate Generator • 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications • • • • • • • 25.2 – 1, 1.
PAGE 563
AT32UC3C ble (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo.
PAGE 564
AT32UC3C 25.3 Block Diagram Figure 25-1. USART Block Diagram Peripheral DMA Controller Channel Channel I/O Controller USART RXD Receiver RTS INTC USART Interrupt TXD Transmitter CTS DTR CLK_USART Power Manager DIV DSR Modem Signals Control CLK_USART/DIV DCD RI CLK BaudRate Generator User Interface Peripheral bus Table 25-1.
PAGE 565
AT32UC3C 25.4 I/O Lines Description Table 25-2.
PAGE 566
AT32UC3C 25.5 25.5.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the I/O Controller lines. The programmer must first program the I/O Controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the I/O Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
PAGE 567
AT32UC3C 25.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: • 5- to 9-bit full-duplex asynchronous serial communication – MSB- or LSB-first – 1, 1.
PAGE 568
AT32UC3C – Full LIN error checking and reporting – Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. – Generation of the Wakeup signal • Test modes – Remote loopback, local loopback, automatic echo 25.6.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.
PAGE 569
AT32UC3C The following formula performs the calculation of the Baud Rate. SelectedClock Baudrate = -------------------------------------------( 8 ( 2 – Over )CD ) This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is the highest possible clock and that OVER is programmed at 1. 25.6.1.2 Baud Rate Calculation Example Table 25-3 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies.
PAGE 570
AT32UC3C ExpectedBaudRate Error = 1 – ⎛ ---------------------------------------------------⎞ ⎝ ActualBaudRate ⎠ 25.6.1.3 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution.
PAGE 571
AT32UC3C In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART CLK pin. No division is active. The value written in BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock CLK or the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the CLK pin.
PAGE 572
AT32UC3C Generator Register (BRGR). The resulting clock can be provided to the CLK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode.
PAGE 573
AT32UC3C 25.6.3 25.6.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (MR).
PAGE 574
AT32UC3C 25.6.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time.
PAGE 575
AT32UC3C Figure 25-8. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA SFD DATA SFD DATA SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd 8 bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT field in the MR register.
PAGE 576
AT32UC3C Figure 25-9. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd Command Sync start frame delimiter SFD Manchester encoded data DATA Txd Data Sync start frame delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the MAN register must be set.
PAGE 577
AT32UC3C The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0.
PAGE 578
AT32UC3C 25.6.3.4 Manchester Decoder When the MAN field in MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in MAN register to configure the length of the preamble sequence.
PAGE 579
AT32UC3C Figure 25-14. Preamble Pattern Mismatch Preamble Mismatch Manchester coding error Manchester encoded data Preamble Mismatch invalid pattern SFD Txd DATA Preamble Length is set to 8 Figure 25-15.
PAGE 580
AT32UC3C Figure 25-16. Manchester Encoded Characters RF Transmission Fup frequency Carrier ASK/FSK Upstream Receiver Upstream Emitter LNA VCO RF filter Demod Serial Configuration Interface control Fdown frequency Carrier bi-dir line Manchester decoder USART Receiver Manchester encoder USART Emitter ASK/FSK downstream transmitter Downstream Receiver PA RF filter Mod VCO control The USART module is configured as a Manchester encoder/decoder.
PAGE 581
AT32UC3C Figure 25-18. FSK Modulator Output 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 25.6.3.6 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit.
PAGE 582
AT32UC3C Figure 25-20.
PAGE 583
AT32UC3C 25.6.3.8 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (MR). The PAR field also enables the Multidrop mode, see ”Multidrop Mode” on page 584. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd.
PAGE 584
AT32UC3C Figure 25-21. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write CR PARE RXRDY 25.6.3.9 Multidrop Mode If the PAR field in the Mode Register (MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1.
PAGE 585
AT32UC3C Figure 25-22. Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write THR TXRDY TXEMPTY Table 25-8 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 25-8. 25.6.3.11 Maximum Timeguard Length Depending on Baud Rate Baud Rate Bit time Timeguard Bit/sec µs ms 1 200 833 212.
PAGE 586
AT32UC3C handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. • Obtain an interrupt while no character is received. This is performed by writing CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.
PAGE 587
AT32UC3C Table 25-9. 25.6.3.12 Maximum Time-out Period (Continued) Baud Rate Bit Time Time-out 56000 18 1 170 57600 17 1 138 200000 5 328 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (CSR).
PAGE 588
AT32UC3C The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored.
PAGE 589
AT32UC3C Figure 25-26. Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the MODE field in the Mode Register (MR) to the value 0x2.
PAGE 590
AT32UC3C 25.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the MODE field in the Mode Register (MR) to the value 0x4 for protocol T = 0 and to the value 0x6 for protocol T = 1. 25.6.4.
PAGE 591
AT32UC3C If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 25-31. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (RHR).
PAGE 592
AT32UC3C The ITERATION bit in CSR can be cleared by writing the Control Register with the RSIT bit at 1. 25.6.4.6 Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field.
PAGE 593
AT32UC3C 25.6.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 25-10. Table 25-10. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 Kb/s 78.13 µs 9.6 Kb/s 19.53 µs 19.2 Kb/s 9.77 µs 38.4 Kb/s 4.88 µs 57.6 Kb/s 3.26 µs 115.2 Kb/s 1.63 µs Figure 25-33 shows an example of character transmission. Figure 25-33.
PAGE 594
AT32UC3C Table 25-11. IrDA Baud Rate Error (Continued) Peripheral Clock 25.6.5.3 Baud Rate CD Baud Rate Error Pulse Time 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.
PAGE 595
AT32UC3C 25.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 25-35. Figure 25-35.
PAGE 596
AT32UC3C 25.6.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI.
PAGE 597
AT32UC3C 25.6.8 SPI Mode The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
PAGE 598
AT32UC3C 25.6.8.2 Baud Rate In SPI Mode, the baudrate generator operates in the same way as in USART synchronous mode: See Section “25.6.1.4” on page 570. However, there are some restrictions: In SPI Master Mode: • the external clock CLK must not be selected (USCLKS … 0x3), and the bit CLKO must be set to “1” in the Mode Register (MR), in order to generate correctly the serial clock on the CLK pin.
PAGE 599
AT32UC3C 25.6.8.3 Data Transfer Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (MR). The 9 bits are selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI Mode (Master or Slave).
PAGE 600
AT32UC3C Figure 25-37. SPI Transfer Format (CPHA=1, 8 bits per transfer) CLK cycle (for reference) 2 1 4 3 5 7 6 8 CLK (CPOL= 0) CLK (CPOL= 1) MOSI SPI Master ->TXD SPI Slave ->RXD MISO SPI Master ->RXD SPI Slave ->TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB NSS SPI Master ->RTS SPI Slave ->CTS Figure 25-38.
PAGE 601
AT32UC3C 25.6.8.4 Receiver and Transmitter Control See Section “25.6.2” on page 572. 25.6.8.5 Character Transmission The characters are sent by writing in the Transmit Holding Register (THR). An additional condition for transmitting a character can be added when the USART is configured in SPI master mode. In the MR register, the value configured on INACK field can prevent any character transmission (even if THR has been written) while the receiver side is not ready (character not read).
PAGE 602
AT32UC3C 25.6.8.7 Receiver Time-out Because the receiver baudrate clock is active only during data transfers in SPI Mode, a receiver time-out is impossible in this mode, whatever the Time-out value is (field TO) in the Time-out Register (RTOR).
PAGE 603
AT32UC3C 25.6.9 LIN Mode The LIN Mode provides Master node and Slave node connectivity on a LIN bus. The LIN (Local Interconnect Network) is a serial communication protocol which efficiently supports the control of mechatronic nodes in distributed automotive applications. The main properties of the LIN bus are: • Single Master/Multiple Slaves concept • Low cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software, or as a pure state machine.
PAGE 604
AT32UC3C 25.6.9.6 Header Transmission (Master Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. So in Master node configuration, the frame handling starts with the sending of the header. The header is transmitted as soon as the identifier is written in the LIN Identifier register (LINIR). At this moment the flag TXRDY falls.
PAGE 605
AT32UC3C 25.6.9.7 Header Reception (Slave Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. In Slave node configuration, the frame handling starts with the reception of the header. The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break Field.
PAGE 606
AT32UC3C The time measurement is made by a 19-bit counter clocked by the sampling clock (see Section 25.6.1). When the start bit of the Synch Field is detected the counter is reset. Then during the next 8 Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is stopped.
PAGE 607
AT32UC3C ⎛ ⎞ ⎜ [ α × 8 × ( 2 – Over ) + β ] × Baudrate⎟ -------------------------------------------------------------------------------------------Baudrate_deviation = ⎜ 100 × ⎟% F TOL_UNSYNCH ⎜ ⎟ ⎛ ⎞ -------------------------------------8× xF ⎝ ⎠ ⎝ ⎠ Nom 100 – 0.5 ≤ α ≤ +0.5 -1 < β < +1 FTOL_UNSYNCH is the deviation of the real slave node clock from the nominal clock frequency. The LIN Standard imposes that it must not exceed ±15%.
PAGE 608
AT32UC3C • PARDIS = 0: During header transmission, the parity bits are computed and sent with the 6 least significant bits of the IDCHR field of the LIN Identifier register (LINIR). The bits 6 and 7 of this register are discarded. During header reception, the parity bits of the identifier are checked. If the parity bits are wrong, an Identifier Parity error occurs (see Section 25.6.3.8). Only the 6 least significant bits of the IDCHR field are updated with the received Identifier.
PAGE 609
AT32UC3C • Data transfer from the Slave2 to the Master and to the Slave1: NACT(Master)=SUBSCRIBE NACT(Slave1)=SUBSCRIBE NACT(Slave2)=PUBLISH 609 32117D–AVR-01/12
PAGE 610
AT32UC3C 25.6.9.11 Response Data Length The LIN response data length is the number of data fields (bytes) of the response excluding the checksum. The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier (compatibility to LIN Specification 1.1).
PAGE 611
AT32UC3C 25.6.9.12 Checksum The last field of a frame is the checksum. The checksum contains the inverted 8- bit sum with carry, over all data bytes or all data bytes and the protected identifier. Checksum calculation over the data bytes only is called classic checksum and it is used for communication with LIN 1.3 slaves. Checksum calculation over the data bytes and the protected identifier byte is called enhanced checksum and it is used for communication with LIN 2.0 slaves.
PAGE 612
AT32UC3C 25.6.9.13 Frame Slot Mode This mode is useful only for Master nodes. It respects the following rule: each frame slot shall be longer than or equal to TFrame_Maximum. If the Frame Slot Mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set again only after TFrame_Maximum delay, from the start of frame. So the Master node cannot send a new header if the frame slot duration of the previous frame is inferior to TFrame_Maximum.
PAGE 613
AT32UC3C 25.6.10 25.6.10.1 LIN Errors Bit Error This error is generated when USART is transmitting and if the transmitted value on the Tx line is different from the value sampled on the Rx line. If a bit error is detected, the transmission is aborted at the next byte border. This error is reported by LINBE in the Channel Status Register (CSR). 25.6.10.2 Inconsistent Synch Field Error This error is generated if the Synch Field character received is other than 0x55. This error is reported by CSR.
PAGE 614
AT32UC3C 25.6.11 25.6.11.1 LIN Frame Handling Master Node Configuration • Write TXEN and RXEN in CR to enable both the transmitter and the receiver. • Write MODE in MR to select the LIN mode and the Master Node configuration. • Write CD and FP in BRGR to configure the baud rate. • Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM, FSDIS and DLC in LINMR to configure the frame transfer.
PAGE 615
AT32UC3C Figure 25-45. Master Node Configuration, NACT = PUBLISH Frame slot = TFrame_Maximum Frame Header Break Synch Data3 Interframe space Response space Protected Identifier Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write LINIR Write THR Data 1 Data 2 Data 3 Data N LINTC Figure 25-46.
PAGE 616
AT32UC3C Figure 25-47. Master Node Configuration, NACT=IGNORE Frame slot = TFrame_Maximum Frame Break Response space Header Data3 Synch Protected Identifier Interframe space Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write LINIR LINTC 25.6.11.2 Slave Node Configuration • Write TXEN and RXEN in CR to enable both the transmitter and the receiver. • Write MODE in MR to select the LIN mode and the Slave Node configuration.
PAGE 617
AT32UC3C • Case 3: NACT = IGNORE, the USART is not concerned by the response – Wait until LINTC in CSR rises – Check the LIN errors Figure 25-48. Slave Node Configuration, NACT = PUBLISH Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum Data N Checksum TXRDY RXRDY LINIDRX Read LINID Write THR Data 1 Data 2 Data 3 Data N LINTC Figure 25-49.
PAGE 618
AT32UC3C 25.6.12 LIN Frame Handling With The Peripheral DMA Controller The USART can be used in association with the Peripheral DMA Controller in order to transfer data directly into/from the on- and off-chip memories without any processor intervention. The Peripheral DMA Controller uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The Peripheral DMA Controller always writes in the Transmit Holding register (THR) and it always reads in the Receive Holding register (RHR).
PAGE 619
AT32UC3C Figure 25-52. Master Node with Peripheral DMA Controller (PDCM=0) WRITE BUFFER DATA 0 Peripheral bus DATA 1 NODE ACTION = SUBSCRIBE Peripheral bus READ BUFFER Peripheral DMA Controller | | | | NODE ACTION = PUBLISH RXRDY USART LIN CONTROLLER DATA 0 Peripheral DMA Controller RXRDY USART LIN CONTROLLER TXRDY | | | | DATA N DATA N 25.6.12.2 Slave Node Configuration In this configuration, the Peripheral DMA Controller transfers only the DATA.
PAGE 620
AT32UC3C 25.6.13 Wake-up Request Any node in a sleeping LIN cluster may request a wake-up. In the LIN 2.0 specification, the wakeup request is issued by forcing the bus to the dominant state from 250 µs to 5 ms. For this, it is necessary to send the character 0xF0 in order to impose 5 successive dominant bits. Whatever the baud rate is, this character respects the specified timings.
PAGE 621
AT32UC3C 25.6.14 Bus Idle Time-out If the LIN bus is inactive for a certain duration, the slave nodes shall automatically enter in sleep mode. In the LIN 2.0 specification, this time-out is fixed at 4 seconds. In the LIN 1.3 specification, it is fixed at 25000 Tbits. In Slave Node configuration, the Receiver Time-out detects an idle condition on the RXD line.
PAGE 622
AT32UC3C 25.6.15 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 25.6.15.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 25-54. Normal Mode Configuration RXD Receiver TXD Transmitter 25.6.15.
PAGE 623
AT32UC3C 25.6.15.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 25-57. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 25-57.
PAGE 624
AT32UC3C 25.6.16 Write Protection Registers To prevent any single software error that may corrupt USART behavior, certain address spaces can be write-protected by setting the WPEN bit in the USART Write Protect Mode Register (WPMR). If a write access to the protected registers is detected, then the WPVS flag in the USART Write Protect Status Register (WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
PAGE 625
AT32UC3C 25.7 User Interface Table 25-16.
PAGE 626
AT32UC3C 25.7.1 Name: Control Register CR Access Type: Write-only Offset: 0x0 Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 LINWKUP 20 LINABT 19 RTSDIS/RCS 18 RTSEN/FCS 17 DTRDIS 16 DTREN 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • LINWKUP: Send LIN Wakeup Signal • • • • • • 0: No effect: 1: Sends a wakeup signal on the LIN bus.
PAGE 627
AT32UC3C • RSTNACK: Reset Non Acknowledge • • • • • • • • • • • • 0: No effect 1: Resets NACK in CSR. RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in CSR. No effect if the ISO7816 is not enabled. SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the THR is sent with the address bit set. STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in CSR.
PAGE 628
AT32UC3C 25.7.2 Name: Mode Register MR Access Type: Read-write Offset: 0x4 Reset Value: - 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 INVDATA 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF/CPOL 15 14 13 12 11 10 PAR 9 8 SYNC/CPHA 4 3 2 1 0 CHMODE 7 NBSTOP 6 5 CHRL USCLKS MODE This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register (if exists).
PAGE 629
AT32UC3C • INACK: Inhibit Non Acknowledge • • • • • 0: The NACK is generated. 1: The NACK is not generated. Note: in SPI master mode, if INACK = 0 the character transmission starts as soon as character is written into THR register (assuming TXRDY was set). When INACK = 1, an additional condition must be met. The character transmission starts when a character is written and only if RXRDY bit is cleared (RHR has been read). OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling.
PAGE 630
AT32UC3C • PAR: Parity Type Table 25-19. PAR Parity Type 0 0 0 Even parity 0 0 1 Odd parity 0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multidrop mode • SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase If USART does not operate in SPI Mode (MODE is … 0xE and 0xF): SYNC = 0: USART operates in Asynchronous Mode. SYNC = 1: USART operates in Synchronous Mode.
PAGE 631
AT32UC3C • MODE Table 25-22.
PAGE 632
AT32UC3C 25.7.3 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x8 Reset Value: - 31 LINHTE 30 LINSTE 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 MANEA 23 – 22 – 21 – 20 MANE 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 LINTC 14 LINID 13 NACK/LINBK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect.
PAGE 633
AT32UC3C 25.7.4 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0xC Reset Value: - 31 LINHTE 30 LINSTE 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 MANEA 23 – 22 – 21 – 20 MANE 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 LINTC 14 LINID 13 NACK/LINBK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect.
PAGE 634
AT32UC3C 25.7.5 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x10 Reset Value: - 31 LINHTE 30 LINSTE 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 MANEA 23 – 22 – 21 – 20 MANE 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 LINTC 14 LINID 13 NACK/LINBK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 635
AT32UC3C 25.7.
PAGE 636
AT32UC3C • • • • • • • • • • • • • • • 0: LIN Bus Line is at 0. 1: LIN Bus Line is at 1. DCD: Image of DCD Input 0: DCD is at 0. 1: DCD is at 1. DSR: Image of DSR Input 0: DSR is at 0. 1: DSR is at 1. RI: Image of RI Input 0: RI is at 0. 1: RI is at 1. CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of CSR. 1: At least one input change has been detected on the CTS pin since the last read of CSR.
PAGE 637
AT32UC3C • • • • • 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA.
PAGE 638
AT32UC3C 25.7.7 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. • RXCHR: Received Character Last character received if RXRDY is set.
PAGE 639
AT32UC3C 25.7.8 Name: USART Transmit Holding Register THR Access Type: Write-only Offset: 0x1C Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command.
PAGE 640
AT32UC3C 25.7.9 Name: Baud Rate Generator Register BRGR Access Type: Read-write Offset: 0x20 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register. • FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8.
PAGE 641
AT32UC3C 25.7.10 Name: Receiver Time-out Register RTOR Access Type: Read-write Offset: 0x24 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 TO 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register. • TO: Time-out Value 0: The Receiver Time-out is disabled.
PAGE 642
AT32UC3C 25.7.11 Name: Transmitter Timeguard Register TTGR Access Type: Read-write Offset: 0x28 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register. • TG: Timeguard Value 0: The Transmitter Timeguard is disabled.
PAGE 643
AT32UC3C 25.7.12 Name: FI DI RATIO Register FIDI Access Type: Read-write Offset: 0x40 Reset Value: 0x00000174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register.
PAGE 644
AT32UC3C 25.7.13 Name: Number of Errors Register NER Access Type: Read-only Offset: 0x44 Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
PAGE 645
AT32UC3C 25.7.14 Name: IrDA FILTER Register IFR Access Type: Read-write Offset: 0x4C Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register (if exists). IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
PAGE 646
AT32UC3C 25.7.15 Name: Manchester Configuration Register MAN Access Type: Read-write Offset: 0x50 Reset Value: 0x30011004 31 – 30 DRIFT 29 1 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 17 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 7 – 6 – 5 – 4 – 3 2 24 RX_PP 16 RX_PL 9 8 TX_PP 1 0 TX_PL This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register (if exists).
PAGE 647
AT32UC3C • TX_PP: Transmitter Preamble Pattern Table 25-25.
PAGE 648
AT32UC3C 25.7.16 Name: LIN Mode Register LINMR Access Type: Read-write Offset: 0x54 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SYNCDIS 16 PDCM 15 14 13 12 11 10 9 8 3 CHKDIS 2 PARDIS 1 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP 0 NACT • SYNCDIS: Synchronization Disable • • • • • • • • 0: The Synchronization procedure is performed in LIN Slave node configuration. 1: The Synchronization procedure is not performed.
PAGE 649
AT32UC3C • NACT: LIN Node Action Table 1. NACT Mode Description 0 0 PUBLISH: The USART transmits the response. 0 1 SUBSCRIBE: The USART receives the response. 1 0 IGNORE: The USART does not transmit and does not receive the response.
PAGE 650
AT32UC3C 25.7.17 Name: LIN Identifier Register LINIR Access Type: Read-write or Read-only Offset: 0x58 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IDCHR • IDCHR: Identifier Character If MODE=0xA (Master node configuration): IDCHR is Read-write and its value is the Identifier character to be transmitted.
PAGE 651
AT32UC3C 25.7.
PAGE 652
AT32UC3C 25.7.19 Write Protect Mode Register Register Name: WPMR Access Type: Read-write Offset: 0xE4 Reset Value: See Table 25-16 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 — 6 — 5 — 4 — • WPKEY: Write Protect KEY Should be written at value 0x555341 ("USA" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
PAGE 653
AT32UC3C 25.7.20 Write Protect Status Register Register Name: WPSR Access Type: Read-only Offset: 0xE8 Reset Value: See Table 25-16 31 — 30 — 29 — 28 — 27 — 26 — 25 — 24 — 23 22 21 20 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 — 6 — 5 — 4 — • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted.
PAGE 654
AT32UC3C 25.7.21 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 18 17 16 15 – 14 – 13 – 12 – 11 9 8 7 6 5 4 1 0 MFN 10 VERSION 3 2 VERSION • MFN Reserved. No functionality associated. • VERSION Version of the module. No functionality associated.
PAGE 655
AT32UC3C 25.8 Module Configuration The specific configuration for each USART instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 25-26.
PAGE 656
AT32UC3C 25.8.2 Register Reset Values Table 25-29.
PAGE 657
AT32UC3C 26. Serial Peripheral Interface (SPI) Rev: 2.1.1.3 26.
PAGE 658
AT32UC3C 26.3 Block Diagram Figure 26-1. SPI Block Diagram Peripheral DMA Controller Peripheral Bus SPCK MISO CLK_SPI MOSI Spi Interface I/O Controller NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 26.4 Application Block Diagram Figure 26-2.
PAGE 659
AT32UC3C 26.5 I/O Lines Description Table 26-1. I/O Lines Description Type 26.6 Pin Name Pin Description Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 26.6.
PAGE 660
AT32UC3C 26.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two bits determine the edges of the clock signal on which data is driven and sampled.
PAGE 661
AT32UC3C Figure 26-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) 1 2 3 4 5 6 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) *** MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB NSS (to slave) *** Not Defined, but normaly LSB of previous character transmitted 26.7.3 Master Mode Operations When configured in master mode, the SPI uses the internal programmable baud rate generator as clock source.
PAGE 662
AT32UC3C Figure 26-5 on page 662shows a block diagram of the SPI when operating in master mode. Figure 26-6 on page 663 shows a flow chart describing how transfers are handled. 26.7.3.1 Master mode block diagram Figure 26-5. Master Mode Block Diagram CSR0..3 SCBR CLK_SPI Baud Rate Generator SPCK SPI Clock RXFIFOEN RDR RDRF OVRES RD CSR0..3 BITS NCPHA CPOL LSB MISO 0 1 Shift Register TDR 4 – Character FIFO MSB TD MOSI TDRE RXFIFOEN RDR CSR0..
PAGE 663
AT32UC3C 26.7.3.2 Master mode flow diagram Figure 26-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
PAGE 664
AT32UC3C 26.7.3.3 Clock generation The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255. This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud rate of CLK_SPI divided by 255. Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbidden. Triggering a transfer while CSRn.SCBR is zero can lead to unpredictable results. At reset, CSRn.
PAGE 665
AT32UC3C 26.7.3.5 Peripheral selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer.
PAGE 666
AT32UC3C to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip Select Active After Transfer bit written to one (CSRn.CSAAT) . This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. When the CSRn.
PAGE 667
AT32UC3C Figure 26-8. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE NPCS[0..3] CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write TDR TDRE NPCS[0..3] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write TDR TDRE NPCS[0..3] DLYBCT DLYBCT A B B A DLYBCS DLYBCS PCS = B PCS = B Write TDR CSAAT = 0 and CSNAAT = 0 CSAAT = 0 and CSNAAT = 1 DLYBCT DLYBCT TDRE NPCS[0..
PAGE 668
AT32UC3C register (MR.MODFDIS). In systems with open-drain I/O lines, a mode fault is detected when a low level is driven by an external master on the NPCS0/NSS signal. When a mode fault is detected, the Mode Fault Error bit in the SR (SR.MODF) is set until the SR is read and the SPI is automatically disabled until re-enabled by writing a one to the SPI Enable bit in the CR register (CR.SPIEN). By default, the mode fault detection circuitry is enabled.
PAGE 669
AT32UC3C Figure 26-9.
PAGE 670
AT32UC3C 26.8 User Interface Table 26-3.
PAGE 671
AT32UC3C 26.8.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - LASTXFER 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - FLUSHFIFO 7 6 5 4 3 2 1 0 SWRST - - - - - SPIDIS SPIEN • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.
PAGE 672
AT32UC3C 26.8.2 Name: Mode Register MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 DLYBCS 23 22 21 20 - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 LLB RXFIFOEN - MODFDIS - PCSDEC PS MSTR PCS • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
PAGE 673
AT32UC3C 0: The FIFO is not used in reception (only one character can be stored in the SPI). • MODFDIS: Mode Fault Detection 1: Mode fault detection is disabled. If the I/O controller does not have open-drain capability, mode fault detection must be disabled for proper operation of the SPI. 0: Mode fault detection is enabled. • PCSDEC: Chip Select Decode 0: The chip selects are directly connected to a peripheral device. 1: The four chip select lines are connected to a 4- to 16-bit decoder.
PAGE 674
AT32UC3C 26.8.3 Name: Receive Data Register RDR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RD[15:8] 7 6 5 4 RD[7:0] • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
PAGE 675
AT32UC3C 26.8.4 Name: Transmit Data Register TDR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - LASTXFER 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD[15:8] 7 6 5 4 TD[7:0] • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.
PAGE 676
AT32UC3C 26.8.5 Name: Status Register SR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - SPIENS 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF • SPIENS: SPI Enable Status 1: This bit is set when the SPI is enabled. 0: This bit is cleared when the SPI is disabled.
PAGE 677
AT32UC3C 26.8.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 678
AT32UC3C 26.8.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 679
AT32UC3C 26.8.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 680
AT32UC3C 26.8.9 Name: Chip Select Register 0 CSR0 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
PAGE 681
AT32UC3C • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
PAGE 682
AT32UC3C CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
PAGE 683
AT32UC3C 26.8.10 Name: Chip Select Register 1 CSR1 Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
PAGE 684
AT32UC3C • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
PAGE 685
AT32UC3C CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
PAGE 686
AT32UC3C 26.8.11 Name: Chip Select Register 2 CSR2 Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
PAGE 687
AT32UC3C • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
PAGE 688
AT32UC3C CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
PAGE 689
AT32UC3C 26.8.12 Name: Chip Select Register 3 CSR3 Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
PAGE 690
AT32UC3C • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
PAGE 691
AT32UC3C CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
PAGE 692
AT32UC3C 26.8.
PAGE 693
AT32UC3C 26.8.
PAGE 694
AT32UC3C 26.8.15 Features Register Register Name: FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - SWIMPL FIFORIMPL BRPBHSB CSNAATIMPL EXTDEC 15 14 13 12 11 10 9 8 LENNCONF 7 6 5 4 PHZNCONF PHCONF PPNCONF PCONF LENCONF 3 2 1 0 NCS • SWIMPL: Spurious Write Protection Implemented • • • • • • • • 0: Spurious write protection is not implemented.
PAGE 695
AT32UC3C • PPNCONF: Polarity Positive if Polarity not Configurable 0: If polarity is not configurable, polarity is negative. 1: If polarity is not configurable, polarity is positive. • PCONF: Polarity Configurable 0: Polarity is not configurable. 1: Polarity is configurable. • NCS: Number of Chip Selects This field indicates the number of chip selects implemented.
PAGE 696
AT32UC3C 26.8.16 Version Register Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 MFN 11 10 VERSION[11:8] 7 6 5 4 3 2 1 0 VERSION[7:0] • MFN Reserved. No functionality associated. • VERSION Version number of the module. No functionality associated.
PAGE 697
AT32UC3C 26.9 Module Configuration The specific configuration for each SPI instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 26-4. SPI Clock Name Module Name Clock Name Description SPI0 CLK_SPI0 Peripheral Bus clock from the PBC clock domain SPI1 CLK_SPI1 Peripheral Bus clock from the PBA clock domain Table 26-5.
PAGE 698
AT32UC3C 27. Two-wire Master Interface (TWIM) Rev.: 1.1.0.1 27.1 Features • Compatible with I²C standard • • • • • • 27.
PAGE 699
AT32UC3C Table 27-2 lists the compatibility level of the Atmel Two-wire Master Interface and a full SMBus compatible master. Table 27-2. 27.3 SMBus Standard Atmel TWIM Bus Timeouts Supported Address Resolution Protocol Supported Alert Supported Host Functionality Supported Packet Error Checking Supported List of Abbreviations Table 27-3. 27.
PAGE 700
AT32UC3C 27.5 Application Block Diagram Figure 27-2. Application Block Diagram VDD Rp Rp Rp TWD TWI Master TWCK TWALM Atmel TWI serial EEPROM I2C RTC I2C LCD controller I2C temp sensor Slave 1 Slave 2 Slave 3 Slave 4 Rp: pull-up value as given by the I2C Standard 27.6 I/O Lines Description Table 27-4. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output TWALM SMBus SMBALERT Input/Output 27.
PAGE 701
AT32UC3C 27.7.3 Clocks The clock for the TWIM bus interface (CLK_TWIM) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TWIM before disabling the clock, to avoid freezing the TWIM in an undefined state. 27.7.4 DMA The TWIM DMA handshake interface is connected to the Peripheral DMA Controller. Using the TWIM DMA functionality requires the Peripheral DMA Controller to be programmed after setting up the TWIM. 27.7.
PAGE 702
AT32UC3C 27.8 27.8.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 27-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 27-4). • A high-to-low transition on the TWD line while TWCK is high defines the START condition.
PAGE 703
AT32UC3C 27.8.2.1 Clock Generation The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK clock. CWGR must be written so that the desired TWI bus timings are generated. CWGR describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be selected through the Clock Prescaler field in CWGR (CWGR.EXP). f CLK_TWIM f PRESCALER = ------------------------( EXP + 1 ) 2 CWGR has the following fields: LOW: Prescaled clock cycles in clock low count.
PAGE 704
AT32UC3C 27.8.2.2 Setting up and Performing a Transfer Operation of the TWIM is mainly controlled by the Control Register (CR) and the Command Register (CMDR). TWIM status is provided in the Status Register (SR). The following list presents the main steps in a typical communication: 1. Before any transfers can be performed, bus timings must be configured by writing to the Clock Waveform Generator Register (CWGR).
PAGE 705
AT32UC3C TWI transfers require the slave to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not acknowledge the data byte.
PAGE 706
AT32UC3C 1. Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state of RHR. Software or the Peripheral DMA Controller must read any data byte present in RHR. 2. Release TWCK generating a clock that the slave uses to transmit a data byte. 3. Place the received data byte in RHR, set RXRDY. 4. If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK. 5. Decrement NBYTES 6. If (NBYTES==0) and STOP=1, transmit STOP condition.
PAGE 707
AT32UC3C 27.8.5 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space to place received data. To assure correct behavior, respect the following programming sequences: 27.8.5.1 Data Transmit with the Peripheral DMA Controller 1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). 2.
PAGE 708
AT32UC3C Figure 27-10. User Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 27-11.
PAGE 709
AT32UC3C As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when data to transmit can be written to THR, or when received data can be read from RHR. Transfer of data to THR and from RHR can also be done automatically by DMA, see Section 27.8.5 27.8.7.1 Write Followed by Write Consider the following transfer: START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+W, DATA+A, DATA+A, STOP. To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2.
PAGE 710
AT32UC3C Figure 27-12. Combining a Write and Read Transfer THR DATA0 DATA1 RHR TWD DATA2 S DADR W A DATA0 A DATA1 NA Sr R DADR A DATA2 A DATA3 DATA3 A P SR.IDLE 1 TXRDY RXRDY To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. 5.
PAGE 711
AT32UC3C 27.8.8 Ten Bit Addressing Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of CMDR.SADR must be written appropriately. In Figure 27-14 and Figure 27-15, the grey boxes represent signals driven by the master, the white boxes are driven by the slave. 27.8.8.1 Master Transmitter To perform a master transmitter transfer: 1.
PAGE 712
AT32UC3C 27.8.9.1 Packet Error Checking Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to CMDR.PECEN enables automatic PEC handling in the current transfer. Transfers with and without PEC can freely be intermixed in the same system, since some slaves may not support PEC. The PEC LFSR is always updated on every bit transmitted or received, so that PEC handling on combined transfers will be correct.
PAGE 713
AT32UC3C 27.8.10 Identifying Bus Events This chapter lists the different bus events, and how they affect bits in the TWIM registers. This is intended to help writing drivers for the TWIM. Table 27-5. Bus Events Event Effect Master transmitter has sent a data byte SR.THR is cleared. Master receiver has received a data byte SR.RHR is set. Start+Sadr sent, no ack received from slave SR.ANAK is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus.
PAGE 714
AT32UC3C 27.9 User Interface Table 27-6.
PAGE 715
AT32UC3C 27.9.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - STOP 7 6 5 4 3 2 1 0 SWRST - SMDIS SMEN - - MDIS MEN • STOP: Stop the Current Transfer Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle.
PAGE 716
AT32UC3C 27.9.2 Name: Clock Waveform Generator Register CWGR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 - 23 29 28 27 26 EXP 22 21 25 24 DATA 20 19 18 17 16 11 10 9 8 3 2 1 0 STASTO 15 14 13 12 HIGH 7 6 5 4 LOW • EXP: Clock Prescaler Used to specify how to prescale the TWCK clock.
PAGE 717
AT32UC3C 27.9.3 Name: SMBus Timing Register SMBTR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 EXP 23 22 21 20 27 26 25 24 - - - - 19 18 17 16 11 10 9 8 3 2 1 0 THMAX 15 14 13 12 TLOWM 7 6 5 4 TLOWS • EXP: SMBus Timeout Clock Prescaler Used to specify how to prescale the TIM and TLOWM counters in SMBTR.
PAGE 718
AT32UC3C 27.9.4 Name: Command Register CMDR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 30 - 23 29 28 - 22 21 20 27 26 25 24 - - ACKLAST PECEN 19 18 17 16 10 9 8 NBYTES 15 14 13 12 11 VALID STOP START REPSAME TENBIT 7 6 5 4 3 SADR[6:0] SADR[9:7] 2 1 0 READ • ACKLAST: ACK Last Master RX Byte 0: Causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed.
PAGE 719
AT32UC3C Write this bit to one if the command in CMDR performs a repeated start to the same slave address as addressed in the previous transfer in order to enter master receiver mode. Write this bit to zero otherwise. • TENBIT: Ten Bit Addressing Mode 0: Use 7-bit addressing mode. 1: Use 10-bit addressing mode. Must not be used when the TWIM is in SMBus mode. • SADR: Slave Address Address of the slave involved in the transfer. Bits 9-7 are don’t care if 7-bit addressing is used.
PAGE 720
AT32UC3C 27.9.5 Name: Next Command Register NCMDR Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 31 30 - 29 28 - 23 22 21 20 27 26 25 24 - - ACKLAST PECEN 19 18 17 16 10 9 8 NBYTES 15 14 13 12 11 VALID STOP START REPSAME TENBIT 7 6 5 4 3 SADR[6:0] SADR[9:7] 2 1 0 READ This register is identical to CMDR. When the VALID bit in CMDR becomes 0, the content of NCMDR is copied into CMDR, clearing the VALID bit in NCMDR.
PAGE 721
AT32UC3C 27.9.6 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
PAGE 722
AT32UC3C 27.9.7 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Data to Transmit Write data to be transferred on the TWI bus here.
PAGE 723
AT32UC3C 27.9.8 Name: Status Register SR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000002 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - MENB 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY • MENB: Master Interface Enable 0: Master interface is disabled. 1: Master interface is enabled.
PAGE 724
AT32UC3C • IDLE: Master Interface is Idle This bit is one when no command is in progress, and no command waiting to be issued. Otherwise, this bit is cleared. • CCOMP: Command Complete This bit is one when the current command has completed successfully. This bit is zero if the command failed due to conditions such as a NAK receved from slave. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
PAGE 725
AT32UC3C 27.9.9 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect.
PAGE 726
AT32UC3C 27.9.10 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect.
PAGE 727
AT32UC3C 27.9.11 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 728
AT32UC3C 27.9.12 Name: Status Clear Register SCR Access Type : Write-only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - - - CCOMP - - - Writing a zero to a bit in this register has no effect.
PAGE 729
AT32UC3C 27.9.
PAGE 730
AT32UC3C 27.9.14 Name: Version Register (VR) VR Access Type: Read-only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION [11:8] 3 2 1 0 VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 731
AT32UC3C 27.10 Module Configuration The specific configuration for each TWIM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 27-7. Module Configuration Feature TWIM0 TWIM1 TWIM2 SMBus ALERT interface Implemented Implemented Not Implemented Table 27-8.
PAGE 732
AT32UC3C 28. Two-wire Slave Interface (TWIS) Rev.: 1.2.0.1 28.1 Features • Compatible with I²C standard • • • • • • 28.
PAGE 733
AT32UC3C Below, Table 28-2 lists the compatibility level of the Atmel Two-wire Slave Interface and a full SMBus compatible device. Table 28-2. 28.3 SMBus Standard Atmel TWIS Bus Timeouts Supported Address Resolution Protocol Supported Alert Supported Packet Error Checking Supported List of Abbreviations Table 28-3. 28.
PAGE 734
AT32UC3C 28.5 Application Block Diagram Figure 28-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI serial EEPROM Slave 1 I²C RTC I²C LCD controller I²C temp. sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 28.6 I/O Lines Description Table 28-4. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output TWALM SMBus SMBALERT Input/Output 28.
PAGE 735
AT32UC3C 28.7.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TWIS, the TWIS will stop functioning and resume operation after the system wakes up from sleep mode. The TWIS is able to wake the system from sleep mode upon address match, see Section 28.8.8 on page 743. 28.7.3 Clocks The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager.
PAGE 736
AT32UC3C Figure 28-4. Transfer Format TWD TWCK Start 28.8.2 Address R/W Ack Data Ack Data Ack Stop Operation The TWIS has two modes of operation: • Slave transmitter mode • Slave receiver mode A master is a device which starts and stops a transfer and generates the TWCK clock. A slave is assigned an address and responds to requests from the master. These modes are described in the following chapters. Figure 28-5.
PAGE 737
AT32UC3C TTOUT: Prescaled clock cycles used to time SMBUS timeout TTIMEOUT. SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time TSU_DAT. EXP: Specifies the clock prescaler setting used for the SMBUS timeouts. Figure 28-6. Bus Timing Diagram t HIGH t LOW S t HD:STA t LOW t SU:DAT t HD:DAT t t 28.8.2.2 t SU:DAT SU:STA SU:STO P Sr Setting Up and Performing a Transfer Operation of the TWIS is mainly controlled by the Control Register (CR).
PAGE 738
AT32UC3C In I²C mode: • The address in CR.ADR is checked for address match if CR.SMATCH is one. • The General Call address is checked for address match if CR.GCMATCH is one. In SMBus mode: • The address in CR.ADR is checked for address match if CR.SMATCH is one. • The Alert Response Address is checked for address match if CR.SMAL is one. • The Default Address is checked for address match if CR.SMDA is one. • The Host Header Address is checked for address match if CR.SMHH is one. 28.8.2.
PAGE 739
AT32UC3C 4. NBYTES is updated. If CR.CUP is one, NBYTES is incremented, otherwise NBYTES is decremented. 5. After each data byte has been transmitted, the master transmits an ACK (Acknowledge) or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the SR.NAK bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been sampled by the TWIS to be HIGH (see Figure 28-9). The NAK indicates that the transfer is finished, and the TWIS will wait for a STOP or REPEATED START.
PAGE 740
AT32UC3C Figure 28-8. Slave Transmitter with Multiple Data Bytes S TWD DADR R A DATA n A DATA n+5 A DATA n+m N P TCOMP TXRDY Write THR (Data n) NBYTES set to m Write THR (Data n+1) Write THR (Data n+m) Last data sent STOP sent by master Figure 28-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF TWD DATA (LSB) N P TWCK SR.NAK SR.BTF t1 t1 t1: (CLK_TWIS period) x 2 28.8.
PAGE 741
AT32UC3C slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse. The SR.RXRDY bit indicates that a data byte is available in the RHR. The RXRDY bit is also used as Receive Ready for the Peripheral DMA Controller receive channel. Figure 28-10. Slave Receiver with One Data Byte TWD S DADR W A DATA A P TCOMP RXRDY Read RHR Figure 28-11.
PAGE 742
AT32UC3C To assure correct behavior, respect the following programming sequences: 28.8.6.1 Data Transmit with the Peripheral DMA Controller 1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). 2. Configure the TWIS (ADR, NBYTES, etc.). 3. Start the transfer by enabling the Peripheral DMA Controller to transmit. 4. Wait for the Peripheral DMA Controller end-of-transmit flag. 5. Disable the Peripheral DMA Controller. 28.8.6.2 Data Receive with the Peripheral DMA Controller 1.
PAGE 743
AT32UC3C enabled when NBYTES reaches zero. NBYTES must therefore be set to the total number of data bytes in the transmission, including the PEC byte. 28.8.7.2 Timeouts The Timing Register (TR) configures the SMBus timeout values. If a timeout occurs, the slave will leave the bus. The SR.SMBTOUT bit is also set. 28.8.7.3 SMBALERT A slave can get the master’s attention by pulling the SMBALERT line low. This is done by writing a one to the SMBus Alert (SMBALERT) bit in CR.
PAGE 744
AT32UC3C Table 28-5. Bus Events Event Effect Start+Sadr on bus, current slave is addressed, corresponding address match enable bit in CR set, SR.STREN and SR.SOAM are set. Correct address match bit in SR is set. SR.TRA updated according to transfer direction (updating is done one CLK_TWIS cycle after address match bit is set). Slave stretches TWCK immediately after transmitting the address ACK bit. TWCK remains stretched until all address match bits in SR have been cleared.
PAGE 745
AT32UC3C 28.9 User Interface Table 28-6.
PAGE 746
AT32UC3C 28.9.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - TENBIT 23 22 21 20 19 18 17 16 ADR[9:8] ADR[7:0] 15 14 13 12 11 10 9 8 SODR SOAM CUP ACK PECEN SMHH SMDA SMBALERT 7 6 5 4 3 2 1 0 SWRST - - STREN GCMATCH SMATCH SMEN SEN • TENBIT: Ten Bit Address Match 0: Disables Ten Bit Address Match. 1: Enables Ten Bit Address Match.
PAGE 747
AT32UC3C • SWRST: Software Reset This bit will always read as 0. Writing a zero to this bit has no effect. Writing a one to this bit resets the TWIS. • STREN: Clock Stretch Enable 0: Disables clock stretching if RHR/THR buffer full/empty. May cause over/underrun. 1: Enables clock stretching if RHR/THR buffer full/empty. • GCMATCH: General Call Address Match 0: Causes the TWIS not to acknowledge the General Call Address. 1: Causes the TWIS to acknowledge the General Call Address.
PAGE 748
AT32UC3C 28.9.2 Name: NBYTES Register NBYTES Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 NBYTES • NBYTES: Number of Bytes to Transfer Writing to this field updates the NBYTES counter. The field can also be read to learn the progress of the transfer.
PAGE 749
AT32UC3C 28.9.3 Name: Timing Register TR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 EXP 23 22 21 20 27 26 25 24 - - - - 19 18 17 16 11 10 9 8 3 2 1 0 SUDAT 15 14 13 12 TTOUT 7 6 5 4 TLOWS • EXP: Clock Prescaler Used to specify how to prescale the SMBus TLOWS counter.
PAGE 750
AT32UC3C 28.9.4 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data Byte When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
PAGE 751
AT32UC3C 28.9.5 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Data Byte to Transmit Write data to be transferred on the TWI bus here.
PAGE 752
AT32UC3C 28.9.6 Name: Packet Error Check Register PECR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PEC • PEC: Calculated PEC Value The calculated PEC value. Updated automatically by hardware after each byte has been transferred. Reset by hardware after a STOP condition.
PAGE 753
AT32UC3C 28.9.7 Name: Status Register SR Access Type: Read-only Offset: 0x18 Reset Value: 0x000000002 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN TRA - TCOMP SEN TXRDY RXRDY • BTF: Byte Transfer Finished This bit is cleared when the corresponding bit in SCR is written to one.
PAGE 754
AT32UC3C • SMBPECERR: SMBus PEC Error This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus PEC error has occurred. • SMBTOUT: SMBus Timeout This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus timeout has occurred. • NAK: NAK Received This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a NAK was received from the master during slave transmitter operation.
PAGE 755
AT32UC3C 28.9.8 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY Writing a zero to a bit in this register has no effect.
PAGE 756
AT32UC3C 28.9.9 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY Writing a zero to a bit in this register has no effect.
PAGE 757
AT32UC3C 28.9.10 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 758
AT32UC3C 28.9.11 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - - - Writing a zero to a bit in this register has no effect.
PAGE 759
AT32UC3C 28.9.
PAGE 760
AT32UC3C 28.9.13 Name: Version Register (VR) VR Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION [11:8] 3 2 1 0 VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 761
AT32UC3C 28.10 Module Configuration The specific configuration for each TWIS instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 28-7. Module Configuration Feature TWIM0 TWIM1 TWIM2 SMBus ALERT interface Implemented Implemented Not Implemented Table 28-8.
PAGE 762
AT32UC3C 29. CAN Interface (CANIF) Version 1.1.0.4 29.1 Features • • • • • • • • • • • 29.2 Supports CAN 2.0A and 2.
PAGE 763
AT32UC3C 29.3 Block Diagram Figure 29-1. CANIF Block Diagram PB TXLINE(0) RXLINE(0) Msg Handling & Filtering RAM Protocol Engine . . . TXLINE(n) RXLINE(n) CANIF CAN clock HSB 29.4 I/O Lines Description Table 29-1. 29.5 I/O Lines Description Pin Name Pin Description Type TXLINE(n) Transmission line of channel n Output RXLINE(n) Reception line of channel n Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below.
PAGE 764
AT32UC3C 29.5.5 Interrupts CANIF interrupt request line is connected to the interrupt controller. Using the CANIF interrupt requires the interrupt controller to be programmed first. 29.5.6 29.6 Debug Operation All CAN channels are disabled when the CPU enters Debug mode. Communication in progress is not stopped. Please refer to the On-Chip Debug chapter in the AVR32UC Technical Reference Manual, and the OCD Module Configuration section, for details. Functional Description 29.6.1 29.6.1.
PAGE 765
AT32UC3C Table 29-2. CAN Parameter Settings Parameter Range CANCFG field PHASE_SEG2 [1..8]TQ PHS2 + 1 Prescaler [2..32] PRES + 1 Sync Jump Width [1..4] SJW + 1 The bit duration is given by the formula: Tbit = (PRS + PHS1 + PHS2 + 4) x (PRES + 1) x PGCLK_CANIF Note: PRES should not be set to 0, therefore CAN clock is at least divided by 2. 29.6.1.2 Sampling method Bits are sampled between PHASE_SEG1 and PHASE_SEG2. By writing the Sampling Method bit (CANCFG.
PAGE 766
AT32UC3C When Overrun Mode is enabled, the MOb is not disabled after a successful reception. Overrun Mode is enabled by writing a one to CANCFG.OVRM. The Overwrite bit in the MOb Status Register (MObSR.OVW) is set if a previously received message has been overwritten. The mode configured by CANCFG.OVRM is used by all MObs configured for reception. 29.6.1.5 Memory pointer Each channel uses a section of RAM for storing messages.
PAGE 767
AT32UC3C The channel mode is not changed when the channel is disabled, i.e. the Fault Confinement Register (CANFC) is not cleared. Therefore, if the channel was in error passive mode before being disabled, it stays in error passive mode when re-enabled. Figure 29-5. Enable and Disable Sequences CAN bus data frame bus idle data frame CANCTRL.CEN CANSR.CES enable request (user write) 29.6.2.
PAGE 768
AT32UC3C According to the CAN specification, a channel can be in error active, error passive or bus off state. The bus state can be read in the CANFC.EMODE field: Table 29-3. Bus State Coding EMODE State 0 error active state 1 error passive state 2 or 3 bus off state This state depends on both transmit and receive counters value (TEC/REC), also available in the CANFC register (see CAN specification for more details). 29.6.2.
PAGE 769
AT32UC3C Figure 29-7.
PAGE 770
AT32UC3C Figure 29-9. Identifier Mask (IDM) 31 - 31 - 30 29 28 RTRM IDEM 30 29 11 10 - 0 Standard format IDM (11 bits) 28 0 RTRM IDEM Extended format IDM (29 bits) Figure 29-10. Data Fields (64 bits) 31 29.6.3.2 24 23 16 15 8 7 0 DB3 DB2 DB1 DB0 @ DB7 DB6 DB5 DB4 @+4 Transmission Once a message has been written into RAM at the address corresponding to the selected MOb, user controls transmission through the MOBCTRL register: • DLC[3:0] field: Data length code i.e.
PAGE 771
AT32UC3C • DIR bit: MOb direction, 0 stands for reception Once a MOb is enabled (by writing to MOBER), an incoming frame is compared (Section 29.6.4) with every MOb enabled for reception in order to select the MOb for storing the frame. User can check if the channel is receiving a frame by reading the CANSR.RS bit. At the end of the successful reception, the complete message (ID + RTR + IDE + DATA bits) is stored in RAM, the MOBESR.MENn bit is cleared and MOBSR.RXOK is set.
PAGE 772
AT32UC3C ID received: IDT: IDM: Comparison: Accepted: 000.0010.1001 b 000.0010.1010 b 111.1111.0000 b 111.1111.- - - - b Y 000.0010.1001 b 000.0100.1000 b 111.1111.0000 b 111.1001.- - - - b N The filtering process scans each MOb enabled and configured for reception, from MOb 0, in order to find the MOb that matches the conditions. The first MOb to match is selected for storing the message once received successfully. If no MOb matches, the message is discarded. 29.6.
PAGE 773
AT32UC3C Figure 29-11. Interrupt Channel Structure CANIMR WKUPIM BERRI M SERRIM CERRI M FERRIM AERRIM BOFFIM WAKE-UP IRQ WKUP AERR FERR CANISR OR CERR ERROR IRQ SERR BERR BUS OFF IRQ BOFF MOBIMR MIM0 CANIMR TXOKIM RXOKIM .. . OR .. . ... OR ... MTXISR ... ... TXOKi MIMi TXOK IRQ TXOK0 RXOKi ...
PAGE 774
AT32UC3C 29.7 User Interface Offsets are relative to the base address allocated to CANIF and the channel number. Figure 29-12. Address Map Overview PB registers RAM space offset ID 0x04 PARAMETER 0x4 IDM 0x08 CANRAMB 0x8 Data[31:0] 0x0C CANCFG 0xC Data[63:32] ... 0x10 ID 0x58 MTXISR 0x14 IDM 0x5C MOBCTRL 0x18 Data[31:0] 0x60 MOBSCR 0x1C Data[63:32] 0x64 MOBSR Channel 0 ... ...
PAGE 775
AT32UC3C Table 29-4.
PAGE 776
AT32UC3C 29.7.1 Name: Version Register VERSION Access type: Read-only Offset: 0x00 Reset Value: - 31 30 - - 23 22 - 29 28 27 26 25 24 18 17 16 9 8 MNCH0 21 20 19 CHNO VARIANT 15 14 13 12 - - - - 7 6 5 4 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • MNCH0: MOb Number Channel #0 Number of MOb for channel 0 (1..32). • CHNO: Channel Number Number of CAN channels (1..5). • Variant: Variant Number Reserved. No functionality associated.
PAGE 777
AT32UC3C 29.7.2 Name: Parameter Register PARAMETER Access type: Read-only Offset: 0x04 Reset Value: - 31 30 - - 23 22 - - 15 14 - - 7 6 - - 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 MNCH4 21 20 19 MNCH3 13 12 11 MNCH2 5 4 3 MNCH1 • MNCH4: MOb Number Channel #4 Number of MOb for channel 4 (0..32). • MNCH3: MOb Number Channel #3 Number of MOb for channel 3 (0..32). • MNCH2: MOb Number Channel #2 Number of MOb for channel 2 (0..32).
PAGE 778
AT32UC3C 29.7.3 Name: RAM Base Address Register CANRAMB Access type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 RAMBASE[31:24] 23 22 21 20 19 RAMBASE[23:16] 15 14 13 12 11 RAMBASE[15:8] 7 6 5 4 3 RAMBASE[7:0] • RAMBASE: RAM Base Address CAN channel RAM base address.
PAGE 779
AT32UC3C 29.7.4 Name: Configuration Register CANCFG Access type: Read/Write Offset: 0x0C Reset Value: 0x00000001 31 30 29 28 27 26 - - - - - OVRM 23 22 21 20 19 18 - - SM 15 14 13 - - 7 6 - - SJW 12 4 24 CMODE 17 16 PRS 11 10 PHS2 5 25 9 8 PHS1 3 2 1 0 PRES • OVRM: Overrun Mode Overrun mode (MOb is not disabled after successful reception, therefore overwrite is possible). • CMODE: Channel Mode 00: Normal mode. 01: Listening mode. 10: Loop back mode.
PAGE 780
AT32UC3C 29.7.5 Name: Control Register CANCTRL Access type: Read/Write Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - WKEN OVRQ CEN INIT • WKEN: Wake-up Enable 0: Wake-up mode disabled. 1: Wake-up mode enabled, any bus activity will set CANISR.WKUP.
PAGE 781
AT32UC3C 29.7.
PAGE 782
AT32UC3C 29.7.
PAGE 783
AT32UC3C 29.7.8 Name: Interrupt Enable Register CANIER Access type: Write-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - TXOKIM 7 6 5 4 3 2 1 0 RXOKIM WKUPIM BERRIM SERRIM CERRIM FERRIM AERRIM BOFFIM Writing a zero to a bit in this register has no effect.
PAGE 784
AT32UC3C 29.7.9 Name: Interrupt Disable Register CANIDR Access type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - TXOKIM 7 6 5 4 3 2 1 0 RXOKIM WKUPIM BERRIM SERRIM CERRIM FERRIM AERRIM BOFFIM Writing a zero to a bit in this register has no effect.
PAGE 785
AT32UC3C 29.7.10 Name: Interrupt Mask Register CANIMR Access type: Read-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - TXOKIM 7 6 5 4 3 2 1 0 RXOKIM WKUPIM BERRIM SERRIM CERRIM FERRIM AERRIM BOFFIM 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 786
AT32UC3C 29.7.11 Name: Interrupt Status Clear Register CANISCR Access type: Write-only Offset: 0x28 Reset Value: 0x00200000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - WKUP BERR SERR CERR FERR AERR BOFF LSMOB • LSMOB: Last Selected MOb Status Clear Write all bits to one to clear Last Selected MOb number. Writing these bits to any other value has no effect.
PAGE 787
AT32UC3C 29.7.12 Name: Interrupt Status Register CANISR Access type: Read-only Offset: 0x2C Reset Value: 0x00200000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - WKUP BERR SERR CERR FERR AERR BOFF LSMOB • LSMOB: Last Selected MOb Status Last selected MOB number (1X: none, 0X: MOb X selected). • WKUP: Wake-up Status 0: No wake-up request detected.
PAGE 788
AT32UC3C 29.7.
PAGE 789
AT32UC3C 29.7.14 Name: MOb Enable Register MOBER Access type: Write-only Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MEN[31:24] 23 22 21 20 MEN[23:16] 15 14 13 12 MEN[15:8] 7 6 5 4 MEN[7:0] • MEN: MOb Enable Writing a bit to zero has no effect. Writing a bit to one will enable the corresponding MOb.
PAGE 790
AT32UC3C 29.7.15 Name: MOb Disable Register MOBDR Access type: Write-only Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MDIS[31:24] 23 22 21 20 MDIS[23:16] 15 14 13 12 MDIS[15:8] 7 6 5 4 MDIS[7:0] • MDIS: MOb Disable Writing a bit to zero has no effect. Writing a bit to one will disable the corresponding MOb.
PAGE 791
AT32UC3C 29.7.16 Name: MOb Enable Status Register MOBESR Access type: Read-only Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MEN[31:24] 23 22 21 20 MEN[23:16] 15 14 13 12 MEN[15:8] 7 6 5 4 MEN[7:0] • MEN: MOb Enable 0: The corresponding MOb is disabled 1: The corresponding MOb is enabled This bit is cleared when the corresponding bit in MOBDR is written to one.
PAGE 792
AT32UC3C 29.7.17 Name: MOb Interrupt Enable Register MOBIER Access type: Write-only Offset: 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MIM[31:24] 23 22 21 20 MIM[23:16] 15 14 13 12 MIM[15:8] 7 6 5 4 MIM[7:0] • MIM: MOb Interrupt Mask Writing a bit to zero has no effect. Writing a bit to one will set the corresponding bit in MOBIMR.
PAGE 793
AT32UC3C 29.7.18 Name: MOb Interrupt Disable Register MOBIDR Access type: Write-only Offset: 0x44 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MIM[31:24] 23 22 21 20 MIM[23:16] 15 14 13 12 MIM[15:8] 7 6 5 4 MIM[7:0] • MIM: MOb Interrupt Mask Writing a bit to zero has no effect. Writing a bit to one will clear the corresponding bit in MOBIMR.
PAGE 794
AT32UC3C 29.7.19 Name: MOb Interrupt Mask Register MOBIMR Access type: Read-only Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MIM[31:24] 23 22 21 20 MIM[23:16] 15 14 13 12 MIM[15:8] 7 6 5 4 MIM[7:0] • MIM: MOb Interrupt Mask 0: The corresponding MOb interrupt is disabled. 1: The corresponding MOb interrupt is enabled. This bit is cleared when the corresponding bit in MOBIDR is written to one.
PAGE 795
AT32UC3C 29.7.20 Name: MOb RX Interrupt Status Clear Register MRXISCR Access type: Write-only Offset: 0x4C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXOK[31:24] 23 22 21 20 RXOK[23:16] 15 14 13 12 RXOK[15:8] 7 6 5 4 RXOK[7:0] • RXOK: Reception Successful Writing a bit to zero has no effect. Writing a bit to one will clear the corresponding bit in MRXISR.
PAGE 796
AT32UC3C 29.7.21 Name: MOb RX Interrupt Status Register MRXISR Access type: Read-only Offset: 0x50 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXOK[31:24] 23 22 21 20 RXOK[23:16] 15 14 13 12 RXOK[15:8] 7 6 5 4 RXOK[7:0] • RXOK: Reception Successful 0: The corresponding MOb has not completed a reception. 1: The corresponding MOb has completed a reception (same bit as MOBSRn.RXOK).
PAGE 797
AT32UC3C 29.7.22 Name: MOb TX Interrupt Status Clear Register MTXISCR Access type: Write-only Offset: 0x54 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXOK[31:24] 23 22 21 20 TXOK[23:16] 15 14 13 12 TXOK[15:8] 7 6 5 4 TXOK[7:0] • TXOK: Transmission successful Writing a bit to zero has no effect. Writing a bit to one will clear the corresponding bit in MTXISR.
PAGE 798
AT32UC3C 29.7.23 Name: MOb TX Interrupt Status Register MTXISR Access type: Read-only Offset: 0x58 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXOK[31:24] 23 22 21 20 TXOK[23:16] 15 14 13 12 TXOK[15:8] 7 6 5 4 TXOK[7:0] • TXOK: Transmission Successful 0: The corresponding MOb has not completed a transmission. 1: The corresponding MOb has completed a transmission (same bit as MOBSRn.TXOK).
PAGE 799
AT32UC3C 29.7.
PAGE 800
AT32UC3C 29.7.25 Name: MOb Status Clear Register MOBSCRn Access type: Write-only Offset: 0x60 + [n * 0xC] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - OVW DLCW TXOK RXOK • OVW: Overwrite Writing this bit to zero has no effect. Writing this bit to one clears the OVW status in MOBSR.
PAGE 801
AT32UC3C 29.7.26 Name: MOb Status Register MOBSRn Access type: Read-only Offset: 0x64 + [n * 0xC] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - OVW DLCW TXOK RXOK • OVW: Overwrite 0: Previous message has not been overwritten. 1: A new message has been received and overwritten previous one (if CANCFG.OVRM is set).
PAGE 802
AT32UC3C 29.8 Module Configuration The specific configuration for each CANIF instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 29-5. Module Configuration Feature CANIF CANIF channels 2 Table 29-6. Module name CANIF Table 29-7.
PAGE 803
AT32UC3C 30. Inter-IC Sound Controller (IISC) Rev.: 2.0.0.0 30.1 Features • Compliant with Inter-IC Sound (I2S) bus specification • Master, slave, and controller modes: • • • • • • 30.
PAGE 804
AT32UC3C 30.3 Block Diagram Figure 30-1. IISC Block Diagram IISC Peripheral DMA Controller Interrupt Controller 30.4 Clocks PB clock PB Rx Tx IRQ Transmitter IWS ISDI ISDO I/O Lines Description Table 30-1. I/O Lines Description Pin Name 30.
PAGE 805
AT32UC3C 30.5.3 Clocks The clock for the IISC bus interface (CLK_IISC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the IISC before disabling the clock, to avoid freezing the IISC in an undefined state. One of the generic clocks is connected to the IISC. The generic clock (GCLK_IISC) can be set to a wide range of frequencies and clock sources. The GCLK_IISC must be enabled and configured before use.
PAGE 806
AT32UC3C The Transmitter can be operated by writing to the Transmitter Holding Register (RHR), whenever the Transmit Ready (TXRDY) bit in the Status Register (SR) is set. Successive values written to THR should correspond to the samples from the left and right audio channels, or from channels 0 to MR.NBCHAN in TDM mode, for the successive frames. The Receive Ready and Transmit Ready bits can be polled by reading the Status Register.
PAGE 807
AT32UC3C 30.6.5 TDM Reception and Transmission Sequence In Time Division Multiplexed (TDM) format, 1 to 8 data words are sent or received within each frame, As in the I2S protocol, data bits are left-adjusted in the channel time slot, with the MSB transmitted first, starting one clock period after the transition on the Word Select line. Each time slot is 32-bit long. Figure 30-3.
PAGE 808
AT32UC3C The Master Clock (IMCK) frequency is 8*(NBCHAN+1)*(IMCKFS+1) times the sample frequency (fs), i.e. IWS frequency. The Serial Clock (ISCK) frequency is (NBCHAN+1)*Slot Length times the sample frequency (fs), where Slot Length is defined in Table 30-2 on page 808. Table 30-2. Slot Length MR.DATALENGTH Word Length Slot Length 0 32 bits 32 1 24 bits 2 20 bits 3 18 bits 4 16 bits 5 16 bits compact stereo 6 8 bits 7 8 bits compact stereo 32 if MR.IWS24 is zero 24 if MR.
PAGE 809
AT32UC3C Figure 30-4. IISC Clocks Generation CR.CKEN/CKDIS MR.IMCKMODE Clock enable GCLK_IISC IMCK pin output Clock divider MR.IMCKMODE 0 MR.IMCKFS MR.DATALENGTH 1 ISCK pin output CR.CKEN/CKDIS 0 ISCK pin input 1 Internal bit clock Clock enable Clock divider MR.MODE = SLAVE MR.DATALENGTH IWS pin output 0 IWS pin input 30.6.
PAGE 810
AT32UC3C set and bit i of the TXORCH field in the Status Register is set, where i is the current transmit channel number. If the TXSAME bit in the Mode Register is zero, then a zero data word is transmitted in case of underrun. If MR.TXSAME is one, then the previous data word for the current transmit channel number is transmitted. Data words are right-justified in the RHR and THR registers.
PAGE 811
AT32UC3C Figure 30-5. Interrupt Block Diagram IER Set IMR Clear IDR Transmitter TXRDY TXUR Interrupt Control IISC Interrupt Request Receiver RXRDY RXOR 30.7 IISC Application Examples The IISC can support several serial communication modes used in audio or high-speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the IISC are not listed here. Figure 30-6.
PAGE 812
AT32UC3C Figure 30-7. Codec Application Block Diagram IMCK ISCK IISC IWS ISDO ISDI Master Clock Serial Clock EXTERNAL AUDIO CODEC Frame Sync Serial Data Out Serial Data In Serial Clock Frame Sync First Time Slot Dstart Dend Serial Data Out Serial Data In Figure 30-8.
PAGE 813
AT32UC3C 30.8 User Interface Table 30-3.
PAGE 814
AT32UC3C 30.8.
PAGE 815
AT32UC3C 30.8.2 Name: Mode Register MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 IWS24 IMCKMODE 23 22 28 27 26 25 24 18 17 16 IMCKFS TDMFS 21 20 19 - - - 11 15 14 13 12 - TXSAME TXDMA TXMONO 7 6 5 4 FORMAT 3 - DATALENGTH NBCHAN 10 9 8 RXLOOP RXDMA RXMONO 2 1 0 - MODE The Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS, ISCK, and ISDO outputs.
PAGE 816
AT32UC3C Master Clock to Sampling Frequency (fs) Ratio Table 30-4. IMCKFS fs Ratio 2 channels 4 channels 6 channels 8 channels 256 fs 15 7 - 3 384 fs 23 11 7 5 512 fs 31 15 - 7 768 fs 47 23 15 11 1024 fs 63 31 - 15 • TDMFS: TDM Frame Sync TDM Frame Sync Table 30-5. TDMFS Description 0 SLOT IWS pulse is high for one time slot at beginning of frame 1 HALF IWS pulse is high for half the time slots at beginning of frame, i.e.
PAGE 817
AT32UC3C • FORMAT: I2S or TDM Format Table 30-6.
PAGE 818
AT32UC3C 30.8.3 Name: Status Register SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 - - - - 23 22 21 20 27 14 13 25 24 TXURCH[7:4] TXURCH[3:0] 15 26 12 19 18 17 16 - - - - 11 10 9 8 RXORCH 7 6 5 4 3 2 1 0 - TXUR TXRDY TXEN - RXOR RXRDY RXEN • TXURCH: Transmit Underrun Channel This field is cleared when SCR.
PAGE 819
AT32UC3C 30.8.4 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 - - - - 23 22 21 20 27 14 13 25 24 TXURCH[7:4] TXURCH[3:0] 15 26 12 19 18 17 16 - - - - 11 10 9 8 RXORCH 7 6 5 4 3 2 1 0 - TXUR - - - RXOR - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request.
PAGE 820
AT32UC3C 30.8.5 Name: Status Set Register SSR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 - - - - 23 22 21 20 27 14 13 25 24 TXURCH[7:4] TXURCH[3:0] 15 26 12 19 18 17 16 - - - - 11 10 9 8 RXORCH 7 6 5 4 3 2 1 0 - TXUR - - - RXOR - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in SR.
PAGE 821
AT32UC3C 30.8.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 822
AT32UC3C 30.8.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 823
AT32UC3C 30.8.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 824
AT32UC3C 30.8.9 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RHR[31:24] 23 22 21 20 RHR[23:16] 15 14 13 12 RHR[15:8] 7 6 5 4 RHR[7:0] • RHR: Received Word This field is set by hardware to the last received data word. If MR.DATALENGTH specifies less than 32 bits, data shall be rightjustified into the RHR field.
PAGE 825
AT32UC3C 30.8.10 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 THR[31:24] 23 22 21 20 THR[23:16] 15 14 13 12 THR[15:8] 7 6 5 4 THR[7:0] • THR: Data Word to Be Transmitted Next data word to be transmitted after the current word if TXRDY is not set. If MR.DATALENGTH specifies less than 32 bits, data shall be right-justified into the THR field.
PAGE 826
AT32UC3C 30.8.11 Name: Module Version VERSION Access Type: Read-only Offset: 0x28 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 827
AT32UC3C 30.8.12 Name: Module Parameters PARAMETER Access Type: Read-only Offset: 0x2C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - Reserved. No functionality associated.
PAGE 828
AT32UC3C 30.9 Module configuration The specific configuration for each IISC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 30-9. Module configuration Feature IISC Number of TDM channels 8 channels Number of Peripheral DMA channels 8 channels Table 30-10.
PAGE 829
AT32UC3C 31. Timer/Counter (TC) Rev: 2.2.3.3 31.1 Features • Three 16-bit Timer Counter channels • A wide range of functions including: • • • • 31.
PAGE 830
AT32UC3C 31.3 Block Diagram Figure 31-1.
PAGE 831
AT32UC3C When using the TIOA/TIOB lines as inputs the user must make sure that no peripheral events are generated on the line. Refer to the Peripheral Event System chapter for details. 31.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning and resume operation after the system wakes up from sleep mode. 31.5.3 Clocks The clock for the TC bus interface (CLK_TC) is generated by the Power Manager.
PAGE 832
AT32UC3C The current value of the counter is accessible in real time by reading the Channel n Counter Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 31.6.1.3 Clock selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals A0, A1 or A2 for chaining by writing to the BMR register.
PAGE 833
AT32UC3C 31.6.1.4 Clock control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 31-3 on page 833. • The clock can be enabled or disabled by the user by writing to the Counter Clock Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter Clock Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS).
PAGE 834
AT32UC3C In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 31.6.1.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: • Software Trigger: each channel has a software trigger, available by writing a one to the Software Trigger Command bit in CCRn (CCRn.
PAGE 835
AT32UC3C The RA Loading Selection field in CMRn (CMRn.LDRA) defines the TIOA edge for the loading of the RA register, and the RB Loading Selection field in CMRn (CMRn.LDRB) defines the TIOA edge for the loading of the RB register. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
PAGE 836
32117D–AVR-01/12 TIOA TIOB SYNC MTIOA MTIOB TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 TIMER_CLOCK1 1 Edge Detector ETRGEDG SWTRG CLKI Edge Detector LDRA CLK Trig S R OVF If RA is Loaded CPCTRG 16-bit Counter RESET Q LDBSTOP R S CLKEN Edge Detector LDRB Capture Register A Q CLKSTA LDBDIS Capture Register B CLKDIS SR Timer/Counter Channel If RA is not Loaded or RB is Loaded ABETRG BURST TCCLKS Compare RC = Register C COVFS LDRBS INT AT32UC3C
PAGE 837
AT32UC3C 31.6.3 Waveform Operating Mode Waveform operating mode is entered by writing a one to the CMRn.WAVE bit. In Waveform operating mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event.
PAGE 838
32117D–AVR-01/12 TIOB SYNC XC2 XC1 TIMER_CLOCK5 XC0 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 Edge Detector EEVTEDG SWTRG ENETRG Trig CLK R S Register A Q CLKSTA Compare RA = OVF WAVSEL RESET 16-bit Counter WAVSEL Q SR Timer/Counter Channel EEVT BURST CLKI Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC O utput Contr oller O utput Cont r oller TCCLKS TIOB
PAGE 839
AT32UC3C 31.6.3.2 WAVSEL = 0 When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and the cycle continues. See Figure 31-6 on page 839. An external event trigger or a software trigger can reset the value of CVn. It is important to note that the trigger may occur at any time. See Figure 31-7 on page 840. RC Compare cannot be programmed to generate a trigger in this configuration.
PAGE 840
AT32UC3C Figure 31-7. WAVSEL= 0 With Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples Time TIOB TIOA 31.6.3.3 WAVSEL = 2 When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC, then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then incremented and so on. See Figure 31-8 on page 841.
PAGE 841
AT32UC3C Figure 31-8. WAVSEL = 2 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples Time TIOB TIOA Figure 31-9. WAVSEL = 2 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples Time TIOB TIOA 31.6.3.4 WAVSEL = 1 When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF.
PAGE 842
AT32UC3C A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 31-11 on page 842. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 31-10.
PAGE 843
AT32UC3C 31.6.3.5 WAVSEL = 3 When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See Figure 31-12 on page 843. A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 31-13 on page 844.
PAGE 844
AT32UC3C Figure 31-13. WAVSEL = 3 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC Counter decremented by trigger RB Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 31.6.3.6 External event/trigger conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The External Event Selection field in CMRn (CMRn.EEVT) selects the external trigger.
PAGE 845
AT32UC3C • RB Compare Effect on TIOB (CMRn.BCPB) • RC Compare Effect on TIOA (CMRn.ACPC) • RA Compare Effect on TIOA (CMRn.
PAGE 846
AT32UC3C 31.7 User Interface Table 31-3.
PAGE 847
AT32UC3C Notes: 1. Read-only if CMRn.WAVE is zero. 2. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
PAGE 848
AT32UC3C 31.7.1 Name: Channel Control Register CCR Access Type: Write-only Offset: 0x00 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - SWTRG CLKDIS CLKEN • SWTRG: Software Trigger Command 1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started.
PAGE 849
AT32UC3C 31.7.
PAGE 850
AT32UC3C 0: TIOB is used as an external trigger. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 none 1 rising edge 2 falling edge 3 each edge • LDBDIS: Counter Clock Disable with RB Loading 1: Counter clock is disabled when RB loading occurs. 0: Counter clock is not disabled when RB loading occurs. • LDBSTOP: Counter Clock Stopped with RB Loading 1: Counter clock is stopped when RB loading occurs. 0: Counter clock is not stopped when RB loading occurs.
PAGE 851
AT32UC3C 31.7.
PAGE 852
AT32UC3C • BCPC: RC Compare Effect on TIOB BCPC Effect 0 none 1 set 2 clear 3 toggle • BCPB: RB Compare Effect on TIOB BCPB Effect 0 none 1 set 2 clear 3 toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 none 1 set 2 clear 3 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 none 1 set 2 clear 3 toggle • ACPC: RC Compare Effect on TIOA ACPC Effect 0 none 1 set 2 clear 3 toggle 852 32117D–AVR-01/12
PAGE 853
AT32UC3C • ACPA: RA Compare Effect on TIOA ACPA Effect 0 none 1 set 2 clear 3 toggle • WAVE 1: Waveform mode is enabled. 0: Waveform mode is disabled (Capture mode is enabled).
PAGE 854
AT32UC3C • CPCSTOP: Counter Clock Stopped with RC Compare 1: Counter clock is stopped when counter reaches RC. 0: Counter clock is not stopped when counter reaches RC. • BURST: Burst Signal Selection BURST Burst Signal Selection 0 The clock is not gated by an external signal. 1 XC0 is ANDed with the selected clock. 2 XC1 is ANDed with the selected clock. 3 XC2 is ANDed with the selected clock. • CLKI: Clock Invert 1: Counter is incremented on falling edge of the clock.
PAGE 855
AT32UC3C 31.7.4 Name: Channel Counter Value Register CV Access Type: Read-only Offset: 0x10 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 CV[15:8] 7 6 5 4 CV[7:0] • CV: Counter Value CV contains the counter value in real time.
PAGE 856
AT32UC3C 31.7.5 Name: Channel Register A RA Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x14 + n * 0X40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RA[15:8] 7 6 5 4 RA[7:0] • RA: Register A RA contains the Register A value in real time.
PAGE 857
AT32UC3C 31.7.6 Name: Channel Register B RB Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x18 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RB[15:8] 7 6 5 4 RB[7:0] • RB: Register B RB contains the Register B value in real time.
PAGE 858
AT32UC3C 31.7.7 Name: Channel Register C RC Access Type: Read/Write Offset: 0x1C + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RC[15:8] 7 6 5 4 RC[7:0] • RC: Register C RC contains the Register C value in real time.
PAGE 859
AT32UC3C 31.7.8 Name: Channel Status Register SR Access Type: Read-only Offset: 0x20 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts.
PAGE 860
AT32UC3C • CPBS: RB Compare Status 1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • CPAS: RA Compare Status 1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • LOVRS: Load Overrun Status 1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and CMRn.WAVE is zero.
PAGE 861
AT32UC3C 31.7.9 Name: Channel Interrupt Enable Register IER Access Type: Write-only Offset: 0x24 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect.
PAGE 862
AT32UC3C 31.7.10 Name: Channel Interrupt Disable Register IDR Access Type: Write-only Offset: 0x28 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect.
PAGE 863
AT32UC3C 31.7.11 Name: Channel Interrupt Mask Register IMR Access Type: Read-only Offset: 0x2C + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 864
AT32UC3C 31.7.12 Name: Block Control Register BCR Access Type: Write-only Offset: 0xC0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - SYNC • SYNC: Synchro Command 1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
PAGE 865
AT32UC3C 31.7.
PAGE 866
AT32UC3C • TC0XC0S: External Clock Signal 0 Selection TC0XC0S Signal Connected to XC0 0 TCLK0 1 none 2 TIOA1 3 TIOA2 866 32117D–AVR-01/12
PAGE 867
AT32UC3C 31.7.14 Name: Features Register FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - BRPBHSB UPDNIMPL 7 6 5 4 3 2 1 0 CTRSIZE • BRPBHSB: Bridge type is PB to HSB 1: Bridge type is PB to HSB. 0: Bridge type is not PB to HSB. • UPDNIMPL: Up/down is implemented 1: Up/down counter capability is implemented.
PAGE 868
AT32UC3C 31.7.15 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
PAGE 869
AT32UC3C 31.8 Module Configuration The specific configuration for each TC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 31-4. 31.8.
PAGE 870
AT32UC3C 32. USB Interface (USBC) Rev: 2.1.0.16 32.1 Features • • • • • • • • • • 32.2 Compatible with the USB 2.0 specification Supports full (12Mbit/s) and low (1.
PAGE 871
AT32UC3C The USBC module consists of: • HSB master interface • User interface • USB Core • Transceiver pads Figure 32-1. USBC Block Diagram USB HSB HSB Master USB_VBUS PB (1 DM User Interface USB 2.
PAGE 872
AT32UC3C 32.4 I/O Lines Description Table 32-2. I/O Lines Description PIn Name Pin Description Type Active Level USB_VBOF USB VBUS On/Off: Bus Power Control Port Output USBCON.
PAGE 873
AT32UC3C 32.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 32.5.1 I/O Lines The USBC pins may be multiplexed with the I/O Controller lines. The user must first configure the I/O Controller to assign the desired USBC pins to their peripheral functions. If the USB_ID pin is used the user must also enable its internal pull-up resistor. 32.5.
PAGE 874
AT32UC3C 32.6 Functional Description 32.6.1 USB General Operation 32.6.1.1 Initialization After a hardware reset, the USBC is disabled. When enabled, the USBC runs in either device mode or in host mode according to the ID detection. If the USB_ID pin is not connected to ground and the pull-up is enabled, the USB_ID state bit in the General Status register (USBSTA.ID) will be set and the device mode will be enabled. If a low level is detected on the USB_ID pin, the USBSTA.
PAGE 875
AT32UC3C The USBC can be disabled at any time by writing a zero to USBCON.USBE, this acts as a hardware reset, except that the OTGPADE, VBUSPO, FRZCLK, UIDE, and UIMOD bits in USBCON, and the LS bits in UDCON are not reset. 32.6.1.2 Interrupts One interrupt vector is assigned to the USBC. See Section 32.6.2.18 and Section 32.6.3.16 for further details about device and host interrupts. There are two kinds of general interrupts: processing, i.e.
PAGE 876
AT32UC3C Figure 32-3. Speed Selection in device mode RPU VBUS UDCON.DETACH UDCON.LS DP DM • Host mode When the USBC interface is in host mode, internal pull-downs are enabled on both DP and DM. The interface detects the speed of the connected device and reflects this in the Speed Status field (USBSTA.SPEED). 32.6.1.5 Data management Endpoints and pipe buffers can be allocated anywhere in the embedded memory (CPU RAM or HSB RAM). See ”RAM management” on page 882. 32.6.1.
PAGE 877
AT32UC3C Figure 32-5. Pad events SUSP Suspend detected Cleared on Wakeup WAKEUP Wakeup detected Cleared by software to acknowledge the interrupt PAD state Idle Active Active The Suspend Interrupt bit in the Device Global Interrupt register (UDINT.SUSP) is set and the Wakeup Interrupt (UDINT.WAKEUP) bit is cleared when a USB Suspend state has been detected on the USB bus. This event automatically puts the USB pad in the Idle state.
PAGE 878
AT32UC3C Figure 32-6. Plug-in Detection Input Block Diagram VDD RPU VBUS_pulsing USB_VBUS Session_valid Logic Va_Vbus_valid VBUS VBUSTI RPD USBSTA VBUS_discharge GND Pad Logic The control logic of the USB_VBUS pad outputs two signals: • The Session_valid signal is high when the voltage on the USB_VBUS pad is higher than or equal to 1.4V. • The Va_Vbus_valid signal is high when the voltage on the USB_VBUS pad is higher than or equal to 4.4V. In device mode, the USBSTA.
PAGE 879
AT32UC3C The USBC mode (device or host) can be detected by the USB_ID pin or selected by writing to USBCON.UIMOD. This allows the USB_ID pin to be used as a general purpose I/O pin even when the USBC interface is enabled. The ID Transition Interrupt (IDTI) bit in USBSTA is set on each transition of the ID bit, i.e. when a Mini-A plug (host mode) is connected or disconnected. This does not occur when a Mini-B plug in device mode is connected or disconnected. The USBSTA.
PAGE 880
AT32UC3C 32.6.2 32.6.2.1 USBC Device Mode Operation Device Enabling In device mode, the USBC supports full- and low-speed data transfers. Including the default control endpoint, a total of seven endpoints are provided. They can be configured as isochronous, bulk or interrupt types, as described in Table 32-1 on page 870 After a hardware reset, the USBC device mode is in the reset state (see Section 32.6.1.1).
PAGE 881
AT32UC3C • After all kinds of resets, the USB device address is 0. • The host starts a SETUP transaction with a SET_ADDRESS(addr) request. • The user writes this address to the USB Address field (UDCON.UADD), and writes a zero to the Address Enable bit (UDCON.ADDEN), resulting in the address remaining zero. • The user sends a zero-length IN packet from the control endpoint. • The user enables the stored USB device address by writing a one to ADDEN.
PAGE 882
AT32UC3C • The user may then write a one to the remote wakeup (RMWKUP) bit in UDCON to send an Upstream Resume to the host initiating the wakeup. This will automatically be done by the controller after 5ms of inactivity on the USB bus. • When the controller sends the Upstream Resume, the Upstream Resume (UPRSM) interrupt is set and SUSP is cleared. • RMWKUP is cleared at the end of the transmitting Upstream Resume.
PAGE 883
AT32UC3C Figure 32-8.
PAGE 884
AT32UC3C • The control and status fields for the endpoint and bank (EPn_CTR_STA_BK0/1): Table 32-5. 31:19 EPn_CTR_STA_BK0/1 structure 18 17 16 15:1 Status elements - UNDERF OVERF 0 Control elements CRCERR - STALLRQ_NEXT – UNDERF: Underflow status for isochronous IN transfer. See ”Data flow error” on page 891. – OVERF: Overflow status for isochronous OUT transfer. See ”Data flow error” on page 891. – CRCERR: CRC error status for isochronous OUT transfer. See ”CRC error” on page 891.
PAGE 885
AT32UC3C 32.6.2.12 Multi packet mode and single packet mode. Single packet mode is the default mode where one USB packet is managed per bank. The multi-packet mode allows the user to manage data exceeding the maximum endpoint size (UECFGn.EPSIZE) for an endpoint bank across multiple packets without software intervention. This mode can also be coupled with the ping-pong mode. • For an OUT endpoint, the EPn_PCKSIZE_BK0/1.MULTI_PACKET_SIZE field should be configured correctly to enable the multi-packet mode.
PAGE 886
AT32UC3C Figure 32-9. Control Write SETUP USB Bus DATA SETUP OUT STATUS OUT IN IN NAK RXSTPI HW SW RXOUTI HW SW HW SW TXINI SW • Control read Figure 32-10 on page 886 shows a control read transaction. The USBC has to manage the simultaneous write requests from the CPU and USB host. Figure 32-10.
PAGE 887
AT32UC3C 32.6.2.14 Management of IN endpoints • Overview IN packets are sent by the USBC device controller upon IN requests from the host. The endpoint and its descriptor in RAM must be pre configured (see section ”RAM management” on page 882 for more details). When the current bank is clear, the TXINI and FIFO Control (UECONn.FIFOCON) bits will be set simultaneously. This triggers an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one.
PAGE 888
AT32UC3C • Detailed description The data is written according to this sequence: • When the bank is empty, TXINI and FIFOCON are set, which triggers an EPnINT interrupt if TXINE is one. • The user acknowledges the interrupt by clearing TXINI. • The user reads the UESTAX.CURRBK field to see which the current bank is. • The user writes the data to the current bank, located in RAM as described by its descriptor: EPn_ADDR_BK0/1.
PAGE 889
AT32UC3C set, or if the total byte count is not an integral multiple of EPSIZE, whereby the last packet should be short. To enable the multi packet mode, the user should configure the endpoint descriptor (EPn_PCKSIZE_BK0/1.BYTE_COUNT) to the total size of the multi packet, which should be larger than the endpoint size (EPSIZE). Since the EPn_PCKSIZE_BK0/1.
PAGE 890
AT32UC3C Figure 32-15. Example of an OUT endpoint with two data banks OUT DATA (bank 0) ACK OUT DATA (bank 1) HW RXOUTI ACK HW SW SW read data from CPU BANK 0 FIFOCON SW read data from CPU BANK 1 • Detailed description Before using the OUT endpoint, one should properly initialize its descriptor for each bank. See Figure 32-8 on page 883. The data is read, according to this sequence: • When the bank is full, RXOUTI and FIFOCON are set, which triggers an EPnINT interrupt if RXOUTE is one.
PAGE 891
AT32UC3C • A packet has been successfully received and the updated BYTE_COUNT equals the MULTI_PACKET_SIZE. • A short packet (smaller than EPSIZE) has been received. 32.6.2.16 Data flow error This error exists only for isochronous IN/OUT endpoints. It sets the Errorflow Interrupt (ERRORFI) bit in UESTAn, which triggers an EPnINT interrupt if the Errorflow Interrupt Enable (ERRORFE) bit is one. The user can check the EPn_CTR_STA_BK0/1.
PAGE 892
AT32UC3C • The Start of Frame (SOF) interrupt with a frame number CRC error (FNCERR is one) • Endpoint interrupts The processing device endpoint interrupts are: • The Transmitted IN Data Interrupt (TXINI) • The Received OUT Data Interrupt (RXOUTI) • The Received SETUP Interrupt (RXSTPI) • The Number of Busy Banks (NBUSYBK) interrupt The exception device endpoint interrupts are: • The Errorflow Interrupt (ERRORFI) • The NAKed OUT Interrupt (NAKOUTI) • The NAKed IN Interrupt (NAKINI) • The STALLed Interrupt (
PAGE 893
AT32UC3C 32.6.3 32.6.3.1 USB Host Operation Host Enabling Figure 32-16 on page 893 describes the USBC host mode main states. Figure 32-16. Host mode states Device Disconnection Macro off Clock stopped Idle Device Connection Device Disconnection Ready SOFE = 0 SOFE = 1 Suspend After a hardware reset, the USBC host mode is in the Reset state (see Section 32.6.1.1). When the USBC is enabled (USBCON.USBE = 1) in host mode (USBSTA.
PAGE 894
AT32UC3C Figure 32-17. USB Communication Flow In host mode, the USBC associates a pipe to a device endpoint, according to the device configuration descriptors. 32.6.3.4 USB reset The USBC sends a USB reset signal when the user writes a one to the Send USB Reset bit (UHCON.RESET). When the USB reset has been sent, the USB Reset Sent Interrupt bit in the Host Global Interrupt register (UHINT.RSTI) is set and all the pipes will be disabled. If the bus was previously in a suspended state (UHCON.
PAGE 895
AT32UC3C 32.6.3.7 Remote wakeup Writing UHCON.SOFE to zero when in host mode will cause the USBC to cease sending SOF’s on the USB bus and enter the Suspend state. The USB device will enter the Suspend state 3ms later. The device can awaken the host by sending an Upstream Resume (remote wakeup feature). When the host detects a non-idle state on the USB bus, it sets the Host Wakeup interrupt bit (UHINT.HWUPI).
PAGE 896
AT32UC3C Figure 32-18.
PAGE 897
AT32UC3C • The control and status fields for the pipe and bank (Pn_CTR_STA_BK0/1): Table 32-7. 31:19 Pn_CTR_STA_BK0/1 structure 18 17 16 15:0 Status - UNDERF Control OVERF CRCERR - – UNDERF: Underflow status for isochronous/Interrupt IN transfers. This status bit is set by hardware at the current bank (where the IN packet should have been stored). When a new successful transaction occurs this bit is overwritten to zero if UPSTAX.ERRORFI has previously been cleared by software.
PAGE 898
AT32UC3C – DTGLER: Is set if a Data toggle error occurs during a USB transaction. 32.6.3.9 Multi packet mode and single packet mode. See ”Multi packet mode and single packet mode.” on page 885 and just consider that an OUT pipe corresponds to an IN endpoint, and an IN pipe corresponds to an OUT endpoint. 32.6.3.10 Management of control pipes A control transaction is composed of three stages: • SETUP • Data (IN or OUT) • Status (OUT or IN) The user has to change the pipe token according to each stage.
PAGE 899
AT32UC3C RXINI should always be cleared before clearing FIFOCON to avoid missing an RXINI event. Figure 32-19. Example of an IN pipe with one data bank DATA (bank 0) IN ACK IN DATA (bank 0) HW ACK HW SW RXINI SW read data from CPU BANK 0 FIFOCON read data from CPU BANK 0 SW Figure 32-20.
PAGE 900
AT32UC3C TXOUTI shall be cleared by software to acknowledge the interrupt. This is done by writing a one to the Transmitted OUT Data Interrupt Clear bit (UPCONnCLR.TXOUTIC), which does not affect the pipe FIFO. The user writes the OUT data to the bank referenced to by the PEPn descriptor and allows the USBC to send the data by writing a one to the FIFO Control Clear (UPCONnCLR.FIFOCONC) bit. This will also cause a switch to the next bank if the OUT pipe is composed of multiple banks.
PAGE 901
AT32UC3C Figure 32-23. Example of an OUT pipe with two data banks and a bank switching delay OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW TXOUTI SW FIFOCON SW write data to CPU BANK 0 SW SW write data to CPU BANK 1 SW write data to CPU BANK0 • Multi packet mode for OUT pipes See section ”Multi packet mode for IN endpoints” on page 888 and just replace IN endpoints with OUT pipe. 32.6.3.
PAGE 902
AT32UC3C A CRC error can occur during the IN stage if the USBC detects a corrupted packet. The IN packet will remain stored in the bank and RXINI will be set. The user can check the Pn_CTR_STA_BK0/1.CRCERR bit in the pipe descriptor to see which current bank has been affected. 32.6.3.16 Interrupts There are two kinds of host interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors not related to CPU exceptions.
PAGE 903
AT32UC3C 32.7 User Interface Table 32-10.
PAGE 904
AT32UC3C Table 32-10.
PAGE 905
AT32UC3C 32.7.1 USB General Registers 32.7.1.
PAGE 906
AT32UC3C • • • • • • • • • • • • 1: The USBC is enabled. This bit can be written to even if FRZCLK is one. FRZCLK: Freeze USB Clock Writing a zero to this bit will enable USB clock inputs. Writing a one to this bit will disable USB clock inputs. The resume detection will remain active. Unless explicitly stated, all registers will become read-only. 0: The clock inputs are enabled. 1: The clock inputs are disabled. This bit can be written to even if USBE is zero.
PAGE 907
AT32UC3C 1: The VBUS Error Interrupt (VBERRI) is enabled. • SRPE: SRP Interrupt Enable 0: The SRP Interrupt (SRPI) is disabled. 1: The SRP Interrupt (SRPI) is enabled. • VBUSTE: VBUS Transition Interrupt Enable 0: The VBUS Transition Interrupt (VBUSTI) is disabled. 1: The VBUS Transition Interrupt (VBUSTI) is enabled. • IDTE: ID Transition Interrupt Enable 0: The ID Transition interrupt (IDTI) is disabled. 1: The ID Transition interrupt (IDTI) is enabled.
PAGE 908
AT32UC3C 32.7.1.2 General Status Register Register Name: USBSTA Access Type: Read-Only Offset: 0x0804 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - CLKUSABLE VBUS ID VBUSRQ - 7 6 5 4 3 2 1 0 STOI HNPERRI ROLEEXI BCERRI VBERRI SRPI VBUSTI IDTI SPEED • CLKUSABLE: Generic Clock Usable This bit is cleared when the USB generic clock is not usable.
PAGE 909
AT32UC3C • STOI: Suspend Time-Out Interrupt This bit is cleared when the USBSTACLR.STOIC bit is written to one. This bit is set when a time-out error (more than 200ms) has been detected after a suspend. This triggers a USB interrupt if STOE is one. This bit should only be used in host mode. • HNPERRI: HNP Error Interrupt This bit is cleared when the USBSTACLR.HNPERRIC bit is written to one. This bit is set when an error has been detected during a HNP negotiation.
PAGE 910
AT32UC3C 32.7.1.3 General Status Clear Register Register Name: USBSTACLR Access Type: Write-Only Offset: 0x0808 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - VBUSRQC - 7 6 5 4 3 2 1 0 STOIC HNPERRIC ROLEEXIC BCERRIC VBERRIC SRPIC VBUSTIC IDTIC Writing a zero to a bit in this register has no effect.
PAGE 911
AT32UC3C 32.7.1.4 General Status Set Register Register Name: USBSTASET Access Type: Write-Only Offset: 0x080C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - VBUSRQS - 7 6 5 4 3 2 1 0 STOIS HNPERRIS ROLEEXIS BCERRIS VBERRIS SRPIS VBUSTIS IDTIS Writing a zero to a bit in this register has no effect.
PAGE 912
AT32UC3C 32.7.1.5 Version Register Register Name: UVERS Access Type: Read-Only Offset: 0x0818 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 913
AT32UC3C 32.7.1.
PAGE 914
AT32UC3C 32.7.1.7 Address Size Register Register Name: UADDRSIZE Access Type: Read-Only Offset: 0x0820 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UADDRSIZE[31:24] 23 22 21 20 19 UADDRSIZE[23:16] 15 14 13 12 11 UADDRSIZE[15:8] 7 6 5 4 3 UADDRSIZE[7:0] • UADDRSIZE: IP PB Address Size This field indicates the size of the PB address space reserved for the USBC IP interface.
PAGE 915
AT32UC3C 32.7.1.8 IP Name Register 1 Register Name: UNAME1 Access Type: Read-Only Offset: 0x0824 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UNAME1[31:24] 23 22 21 20 19 UNAME1[23:16] 15 14 13 12 11 UNAME1[15:8] 7 6 5 4 3 UNAME1[7:0] • UNAME1: IP Name Part One This field indicates the first part of the ASCII-encoded name of the USBC IP.
PAGE 916
AT32UC3C 32.7.1.9 IP Name Register 2 Register Name: UNAME2 Access Type: Read-Only Offset: 0x0828 Reset Value: 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UNAME2[31:24] 23 22 21 20 19 UNAME2[23:16] 15 14 13 12 11 UNAME2[15:8] 7 6 5 4 3 UNAME2[7:0] • UNAME2: IP Name Part Two This field indicates the second part of the ASCII-encoded name of the USBC IP.
PAGE 917
AT32UC3C 32.7.1.10 Finite State Machine Status Register Register Name: USBFSM Access Type: Read-Only Offset: 0x082C Reset Value: 0x00000009 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - DRDSTATE • DRDSTATE: Dual Role Device State This field indicates the state of the USBC.
PAGE 918
AT32UC3C DRDSTATE Description 12 b_wait_discharge: In this state, the B-device waits for the data usb line to discharge (100 us) before becoming Host. 13 b_wait_acon: In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. 14 b_host: In this state, the B-device acts as the Host. 15 b_srp_init: In this state, the B-device attempts to start a session using the SRP protocol.
PAGE 919
AT32UC3C 32.7.1.11 USB Descriptor Address Register Name: UDESC Access Type: Read-Write Offset: 0x0830 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UDESCA[31:24] 23 22 21 20 19 UDESCA[23:16] 15 14 13 12 11 UDESCA[15:8] 7 6 5 4 3 UDESCA[7:0] • UDESCA: USB Descriptor Address This field contains the address of the USB descriptor. The three least significant bits are always zero.
PAGE 920
AT32UC3C 32.7.2 USB Device Registers 32.7.2.1 Device General Control Register Register Name: UDCON Access Type: Read/Write Offset: 0x0000 Reset Value: 0x00000100 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - GNAK - 15 14 13 12 11 10 9 8 - - - LS - - RMWKUP DETACH 7 6 5 4 3 2 1 0 ADDEN UADD • GNAK: Global NAK 0: Normal mode.
PAGE 921
AT32UC3C 32.7.2.2 Device Global Interrupt Register Register Name: UDINT Access Type: Read-Only Offset: 0x0004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 18 (1) EP7INT EP6INT 17 (1) EP5INT 16 (1) EP4INT(1) - - - 15 14 13 12 11 10 9 8 EP3INT(1) EP2INT(1) EP1INT(1) EP0INT - - - - 7 6 5 4 3 2 1 0 - UPRSM EORSM WAKEUP EORST SOF - SUSP Note: EP8INT 19 (1) 1.
PAGE 922
AT32UC3C • SUSP: Suspend Interrupt This bit is cleared when the UDINTCLR.SUSPC bit is written to one to acknowledge the interrupt or when the Wakeup (WAKEUP) interrupt bit is set. This bit is set when a USB “Suspend” idle bus state has been detected for 3 frame periods (J state for 3 ms). This triggers a USB interrupt if SUSPE is one.
PAGE 923
AT32UC3C 32.7.2.3 Device Global Interrupt Clear Register Register Name: UDINTCLR Access Type: Write-Only Offset: 0x0008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - UPRSMC EORSMC WAKEUPC EORSTC SOFC - SUSPC Writing a zero to a bit in this register has no effect.
PAGE 924
AT32UC3C 32.7.2.4 Device Global Interrupt Set Register Register Name: UDINTSET Access Type: Write-Only Offset: 0x000C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - UPRSMS EORSMS WAKEUPS EORSTS SOFS - SUSPS Writing a zero to a bit in this register has no effect.
PAGE 925
AT32UC3C 32.7.2.5 Device Global Interrupt Enable Register Register Name: UDINTE Access Type: Read-Only Offset: 0x0010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 (1) EP7INTE 17 (1) EP6INTE 16 (1) EP5INTE EP4INTE(1) - - - 15 14 13 12 11 10 9 8 EP3INTE(1) EP2INTE(1) EP1INTE(1) EP0INTE - - - - 7 6 5 4 3 2 1 0 - UPRSME EORSME WAKEUPE EORSTE SOFE - SUSPE Note: EP8INTE 18 (1) 1.
PAGE 926
AT32UC3C 32.7.2.6 Device Global Interrupt Enable Clear Register Register Name: UDINTECLR Access Type: Write-Only Offset: 0x0014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 (1) EP7INTEC 17 (1) EP6INTEC EP5INTEC 16 (1) EP4INTEC(1) - - - 15 14 13 12 11 10 9 8 EP3INTEC(1) EP2INTEC(1) EP1INTEC(1) EP0INTEC - - - - 7 6 5 4 3 2 1 0 - UPRSMEC EORSMEC WAKEUPEC EORSTEC SOFEC - SUSPEC Note: EP8INTEC 18 (1) 1.
PAGE 927
AT32UC3C 32.7.2.7 Device Global Interrupt Enable Set Register Register Name: UDINTESET Access Type: Write-Only Offset: 0x0018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 (1) EP7INTES 17 (1) EP6INTES 16 (1) EP5INTES EP4INTES(1) - - - 15 14 13 12 11 10 9 8 EP3INTES(1) EP2INTES(1) EP1INTES(1) EP0INTES - - - - 7 6 5 4 3 2 1 0 - UPRSMES EORSMES WAKEUPES EORSTES SOFES - SUSPES Note: EP8INTES 18 (1) 1.
PAGE 928
AT32UC3C 32.7.2.8 Endpoint Enable/Reset Register Register Name: UERST Access Type: Read/Write Offset: 0x001C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - EPEN8(1) 7 6 5 4 3 2 1 0 EPEN7(1) EPEN6(1) EPEN5(1) EPEN4(1) EPEN3(1) EPEN2(1) EPEN1(1) EPEN0 • EPENn: Endpoint n Enable Note: 1. EPENn bits are within the range from EPEN0 to EPEN6.
PAGE 929
AT32UC3C 32.7.2.9 Device Frame Number Register Register Name: UDFNUM Access Type: Read-Only Offset: 0x0020 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 FNCERR - 7 6 2 1 0 - - - FNUM[10:5] 5 FNUM[4:0] 4 3 • FNCERR: Frame Number CRC Error This bit is cleared upon receiving a USB reset. This bit is set when a corrupted frame number is received.
PAGE 930
AT32UC3C 32.7.2.10 Endpoint n Configuration Register Register Name: UECFGn, n in [0..
PAGE 931
AT32UC3C EPSIZE Endpoint Size 1 0 1 256 bytes 1 1 0 512 bytes 1 1 1 1024 bytes This field is cleared upon receiving a USB reset (except for the endpoint 0). • EPBK: Endpoint Banks This bit selects the number of banks for the endpoint: 0: single-bank endpoint 1: double-bank endpoint For control endpoints, a single-bank endpoint shall be selected. This field is cleared upon receiving a USB reset (except for the endpoint 0).
PAGE 932
AT32UC3C 32.7.2.11 Endpoint n Status Register Register Name: UESTAn, n in [0..
PAGE 933
AT32UC3C For IN endpoints, this indicates the number of banks filled by the user and ready for IN transfers. When all banks are free an EPnINT interrupt will be triggered if NBUSYBKE is one. For OUT endpoints, this indicates the number of banks filled by OUT transactions from the host. When all banks are busy an EPnINT interrupt will be triggered if NBUSYBKE is one. • RAMACERI: Ram Access Error Interrupt This bit is cleared when the RAMACERIC bit is written to one, acknowledging the interrupt.
PAGE 934
AT32UC3C This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an EPnINT interrupt if RXOUTE is one. This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full. This triggers an EPnINT interrupt if RXOUTE is one. This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.
PAGE 935
AT32UC3C 32.7.2.12 Endpoint n Status Clear Register Register Name: UESTAnCLR, n in [0..6] Access Type: Write-Only Offset: 0x0160 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - RAMACERIC - - - 7 6 5 4 3 2 1 0 - STALLEDIC/ CRCERRIC - NAKINIC NAKOUTIC RXSTPIC/ ERRORFIC RXOUTIC TXINIC Writing a zero to a bit in this register has no effect.
PAGE 936
AT32UC3C 32.7.2.13 Endpoint n Status Set Register Register Name: UESTAnSET, n in [0..6] Access Type: Write-Only Offset: 0x0190 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - NBUSYBKS RAMACERIS - 7 6 5 4 3 2 1 0 - STALLEDIS/ CRCERRIS - NAKINIS NAKOUTIS RXSTPIS/ ERRORFIS RXOUTIS TXINIS - Writing a zero to a bit in this register has no effect.
PAGE 937
AT32UC3C 32.7.2.14 Endpoint n Control Register Register Name: UECONn, n in [0..
PAGE 938
AT32UC3C • KILLBK: Kill IN Bank • • • • • • • • • • This bit is cleared by hardware after the completion of the “kill packet procedure”. This bit is set when the KILLBKS bit is written to one, killing the last written bank. The user shall wait for this bit to be cleared before trying to process another IN packet. Caution: The bank is cleared when the “kill packet” procedure is completed by the USBC core: If the bank is really killed, the NBUSYBK field is decremented.
PAGE 939
AT32UC3C 32.7.2.15 Endpoint n Control Clear Register Register Name: UECONnCLR, n in [0..
PAGE 940
AT32UC3C 32.7.2.16 Endpoint n Control Set Register Register Name: UECONnSET, n in [0..
PAGE 941
AT32UC3C 32.7.3 USB Host Registers 32.7.3.1 Host General Control Register Register Name: UHCON Access Type: Read/Write Offset: 0x0400 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - RESUME RESET SOFE 7 6 5 4 3 2 1 0 - - - - - - - - • • • RESUME: Send USB Resume Writing a zero to this bit has no effect.
PAGE 942
AT32UC3C 32.7.3.2 Host Global Interrupt Register Register Name: UHINT Access Type: Read-Only Offset: 0x0404 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - P8INT(1) 15 14 13 12 11 10 9 8 P7INT(1) P6INT(1) P5INT(1) P4INT(1) P3INT(1) P2INT(1) P1INT(1) P0INT 7 6 5 4 3 2 1 0 - HWUPI HSOFI RXRSMI RSMEDI RSTI DDISCI DCONNI Note: 1. PnINT bits are within the range from P0INT to P6INT.
PAGE 943
AT32UC3C • DDISCI: Device Disconnection Interrupt This bit is cleared when the DDISCIC bit is written to one. This bit is set when the device has been removed from the USB bus. • DCONNI: Device Connection Interrupt This bit is cleared when the DCONNIC bit is written to one. This bit is set when a new device has been connected to the USB bus.
PAGE 944
AT32UC3C 32.7.3.3 Host Global Interrupt Clear Register Register Name: UHINTCLR Access Type: Write-Only Offset: 0x0408 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - HWUPIC HSOFIC RXRSMIC RSMEDIC RSTIC DDISCIC DCONNIC Writing a zero to a bit in this register has no effect.
PAGE 945
AT32UC3C 32.7.3.4 Host Global Interrupt Set Register Register Name: UHINTSET Access Type: Write-Only Offset: 0x040C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - HWUPIS HSOFIS RXRSMIS RSMEDIS RSTIS DDISCIS DCONNIS - Writing a zero to a bit in this register has no effect.
PAGE 946
AT32UC3C 32.7.3.5 Host Global Interrupt Enable Register Register Name: UHINTE Access Type: Read-Only Offset: 0x0410 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - P8INTE(1) 15 14 13 12 11 10 9 8 P7INTE(1) P6INTE(1) P5INTE(1) P4INTE(1) P3INTE(1) P2INTE(1) P1INTE(1) P0INTE 7 6 5 4 3 2 1 0 - HWUPIE HSOFIE RXRSMIE RSMEDIE RSTIE DDISCIE DCONNIE Note: 1.
PAGE 947
AT32UC3C 32.7.3.6 Host Global Interrupt Enable Clear Register Register Name: UHINTECLR Access Type: Write-Only Offset: 0x0414 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - P8INTEC(1) 15 14 13 12 11 10 9 8 P7INTEC(1) P6INTEC(1) P5INTEC(1) P4INTEC(1) P3INTEC(1) P2INTEC(1) P1INTEC(1) P0INTEC 7 6 5 4 3 2 1 0 - HWUPIEC HSOFIEC RXRSMIEC RSMEDIEC RSTIEC DDISCIEC DCONNIEC Note: 1.
PAGE 948
AT32UC3C 32.7.3.7 Host Global Interrupt Enable Set Register Register Name: UHINTESET Access Type: Write-Only Offset: 0x0418 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - P8INTES(1) 15 14 13 12 11 10 9 8 P7INTES(1) P6INTES(1) P5INTES(1) P4INTES(1) P3INTES(1) P2INTES(1) P1INTES(1) P0INTES 7 6 5 4 3 2 1 0 - HWUPIES HSOFIES RXRSMIES RSMEDIES RSTIES DDISCIES DCONNIES Note: 1.
PAGE 949
AT32UC3C 32.7.3.8 Pipe Enable/Reset Register Register Name: UPRST Access Type: Read/Write Offset: 0x0041C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - PEN8(1) 7 6 5 4 3 2 1 0 PEN7(1) PEN6(1) PEN5(1) PEN4(1) PEN3(1) PEN2(1) PEN1(1) PEN0 Note: 1. PENn bits are within the range from PEN0 to PEN6.
PAGE 950
AT32UC3C 32.7.3.
PAGE 951
AT32UC3C 32.7.3.10 Pipe n Configuration Register Register Name: UPCFGn, n in [0..6] Access Type: Read/Write Offset: 0x0500 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 BINTERVAL 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 3 2 1 0 - PBK - - PTYPE 5 - 4 PSIZE PTOKEN • BINTERVAL: bInterval parameter This field corresponds to the bus access period of the pipe.
PAGE 952
AT32UC3C • PSIZE: Pipe Size This field contains the size of each pipe bank. This field is cleared upon sending a USB reset. PSIZE Endpoint Size 0 0 0 8 bytes 0 0 1 16 bytes 0 1 0 32 bytes 0 1 1 64 bytes 1 0 0 128 bytes 1 0 1 256 bytes 1 1 0 512 bytes 1 1 1 1024 bytes • PBK: Pipe Banks This bit selects the number of banks for the pipe. 0: single-bank pipe 1: double bank pipe For control endpoints, a single-bank pipe should be selected.
PAGE 953
AT32UC3C 32.7.3.11 Pipe n Status Register Register Name: UPSTAn, n in [0..
PAGE 954
AT32UC3C • DTSEQ: Data Toggle Sequence This field indicates the data PID of the current bank. For OUT pipes, this field indicates the data toggle of the next packet that will be sent. For IN pipes, this field indicates the data toggle of the received packet stored in the current bank. DTSEQ Data toggle sequence 0 0 Data0 0 1 Data1 1 0 reserved 1 1 reserved • RXSTALLDI: Received STALLed Interrupt This bit is cleared when the RXSTALLDIC bit is written to one.
PAGE 955
AT32UC3C 32.7.3.12 Pipe n Status Clear Register Register Name: UPSTAnCLR, n in [0..6] Access Type: Write-Only Offset: 0x0560 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - RAMACERIC - - 7 6 5 4 3 2 1 0 - RXSTALLDIC/ CRCERRIC ERRORFIC NAKEDIC PERRIC TXSTPIC TXOUTIC RXINIC Writing a zero to a bit in this register has no effect.
PAGE 956
AT32UC3C 32.7.3.13 Pipe n Status Set Register Register Name: UPSTAnSET, n in [0..6] Access Type: Write-Only Offset: 0x0590 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - RAMACERIS - - 7 6 5 4 3 2 1 0 - RXSTALLDIS/ CRCERRIS ERRORFIC NAKEDIS PERRIS TXSTPIS TXOUTIS RXINIS Writing a zero to a bit in this register has no effect.
PAGE 957
AT32UC3C 32.7.3.14 Pipe n Control Register Register Name: UPCONn, n in [0..
PAGE 958
AT32UC3C This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE). • RAMACERE: Ram Access Error Interrupt Enable This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interrupt (NBUSYBKE). This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE).
PAGE 959
AT32UC3C 32.7.3.15 Pipe n Control Set Register Register Name: UPCONnSET, n in [0..
PAGE 960
AT32UC3C 32.7.3.16 Pipe n Control Clear Register Register Name: UPCONnCLR, n in [0..
PAGE 961
AT32UC3C 32.7.3.17 Pipe n IN Request Register Register Name: UPINRQn, n in [0..6] Access Type: Read/Write Offset: 0x0650 + (n * 0x04) Reset Value: 0x00000001 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - INMODE 7 6 5 4 3 2 1 0 INRQ • INMODE: IN Request Mode Writing a zero to this bit will perform a pre-defined number of IN requests. This number is the INRQ field.
PAGE 962
AT32UC3C 32.8 Module Configuration The specific configuration for each USBC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 32-11. MODULE Clock Name Module name USBC Clock Name Description CLK_USBC_HSB HSB clock CLK_USBC_PB Peripheral Bus clock from the PBB clock domain GCLK_USBC The generic clock used for the USBC is GCLK0 Table 32-12.
PAGE 963
AT32UC3C 33. Pulse Width Modulation Controller (PWM) Rev. 5.0.1.0 33.1 Features • 4 channels • Common clock generator providing thirteen different clocks • • • • • • • 33.
PAGE 964
AT32UC3C The PWM provides 8 independent comparison units capable to compare a programmed value to the counter of the synchronous channels (counter of channel 0). These comparisons are intended to generate software interrupts, to trigger pulses on the 2 independent event lines (in order to synchronize ADC conversions with a lot of flexibility independently of the PWM outputs), and to trigger PDCA transfer requests. The PWM outputs can be overridden synchronously or asynchronously to their channel counter.
PAGE 965
AT32UC3C 33.3 Block Diagram Figure 33-1.
PAGE 966
AT32UC3C 33.4 I/O Lines Description Each channel outputs two complementary external I/O lines. Table 33-1.
PAGE 967
AT32UC3C 33.5 33.5.1 Product Dependencies I/O Lines The pins used for interfacing the PWM may be multiplexed with the I/O Controller lines. The programmer must first program the I/O controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the I/O controller. 33.5.2 Clocks The clock of the PWM (CLK_PWM) is generated by the Power Manager.
PAGE 968
AT32UC3C 33.6 Functional Description The PWM Controller is primarily composed of a clock generator module and 4 channels. • The clock generator module provides 13 clocks. Its source clock is chosen according to the CLKSEL bit in the Clock Register (CLK).
PAGE 969
AT32UC3C The PWM internal clock (named CCK and driven either by CLK_PWM or by GCLK) is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks. The selection of the source clock of the PWM counters is made by the CLKSEL bit in the CLK Register.
PAGE 970
AT32UC3C 33.6.2 PWM Channel 33.6.2.1 Block Diagram Figure 33-3.
PAGE 971
AT32UC3C 33.6.2.2 Comparator The comparator continuously compares its counter value with the channel period defined by CPRD in the ”Channel Period Register” on page 1040 (CPRDx) and the duty-cycle defined by CDTY in the ”Channel Duty Cycle Register” on page 1038 (CDTYx) to generate an output signal OCx accordingly. The different properties of the waveform of the output OCx are: • the clock selection.
PAGE 972
AT32UC3C • the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL field of the CMRx register. By default the signal starts by a low level. • the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the CMRx register. The default mode is left aligned. Figure 33-4.
PAGE 973
AT32UC3C Figure 33-5.
PAGE 974
AT32UC3C 33.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor It is possible to configure a couple of channels to provide a 2-bit gray count waveform on 2 outputs. Dead-Time generator and other downstream logic can be configured on these channels. Up or down count mode can be configured on-the-fly by the SMMR register. When GCEN0 is written to 1, channels 0 and 1 outputs are driven with gray counter. Figure 33-6. 2-bit Gray Up/Down Counter GCEN0 = 1 PWMH0 PWML0 PWMH1 PWML1 DOWNx 33.6.2.
PAGE 975
AT32UC3C Figure 33-7.
PAGE 976
AT32UC3C 33.6.2.5 Output Override The two complementary outputs DTOHx and DTOLx of the dead-time generator can be forced to a value defined by the software. Figure 33-8.
PAGE 977
AT32UC3C 33.6.2.6 Fault Protection 5 inputs provide fault protection which can force any of the PWM output pair to a programmable value. This mechanism has priority over output overriding. Figure 33-9.
PAGE 978
AT32UC3C • To prevent an unexpected activation of the status FSy bit in the FSR register, the FMODy bit can be written to one only if the FPOLy bit has been previously configured to its final value. • To prevent an unexpected activation of the Fault Protection on the channel x, the FPEx[y] bit can be written to one only if the FPOLy bit has been previously configured to its final value. If a comparison unit is enabled (see Section 33.6.
PAGE 979
AT32UC3C 33.6.2.7 Synchronous Channels Some channels can be linked together as synchronous channels. They have the same source clock, the same period, the same alignment and are started together. In this way, their counters are synchronized together. The synchronous channels are defined by the SYNCx bits in the ”Sync Channels Mode Register” on page 1006 (SCM). Only one group of synchronous channels is allowed.
PAGE 980
AT32UC3C 33.6.2.10 on page 984). The user can choose to synchronize the PDCA transfer request with a comparison match (see Section 33.6.3 on page 987), by the PTRM and PTRCS fields in the SCM register. Table 33-2.
PAGE 981
AT32UC3C 33.6.2.8 Method 1: Manual write of duty-cycle values and manual trigger of the update In this mode, the update of the period value, the duty-cycle values and the dead-time values must be made by writing in their respective update registers with the CPU (respectively CPRDUPDx, CDTYUPDx and DTUPDx).
PAGE 982
AT32UC3C 33.6.2.9 Method 2: Manual write of duty-cycle values and automatic trigger of the update In this mode, the update of the period value, the duty-cycle values, the dead-time values and the update period value must be made by writing in their respective update registers with the CPU (respectively CPRDUPDx, CDTYUPDx, DTUPDx and SCUPUPD).
PAGE 983
AT32UC3C Figure 33-11.
PAGE 984
AT32UC3C 33.6.2.10 Method 3: Automatic write of duty-cycle values and automatic trigger of the update In this mode, the update of the duty cycle values is made automatically by the Peripheral DMA Controller (PDCA). The update of the period value, the dead-time values and the update period value must be made by writing in their respective update registers with the CPU (respectively CPRDUPDx, DTUPDx and SCUPUPD).
PAGE 985
AT32UC3C Sequence for Method 3: 1. Select the automatic write of duty-cycle values and automatically update by setting the UPDM field to 2 in the SCM register. 2. Define the synchronous channels by the SYNCx bits in the SCM register. 3. Define the update period by the UPR field in the SCUP register. 4.
PAGE 986
AT32UC3C Figure 33-12. Method 3 (UPDM=2 and PTRM=0) CCNT0 CDTYUPD UPRUPD 0x1 UPR 0x1 UPRCNT 0x0 CDTY 0x60 0x40 0x20 0x80 0xB0 0xA0 0x3 0x3 0x1 0x0 0x1 0x0 0x1 0x1 0x2 0x3 0x0 0x1 0x80 0x60 0x40 0x20 0x0 0x2 0xA0 PDC transfer request WRDY Figure 33-13.
PAGE 987
AT32UC3C 33.6.3 PWM Comparison Units The PWM provides 8 independent comparison units able to compare a programmed value with the current value of the channel 0 counter (which is the channel counter of all synchronous channels, Section 33.6.2.7 on page 979). These comparisons are intended to generate pulses on the event lines (used to synchronize ADC, see Section 33.6.4 on page 989), to generate software interrupts and to trigger PDCA transfer requests for the synchronous channels (see Section 33.6.2.
PAGE 988
AT32UC3C The update of the comparison x configuration and the comparison x value is triggered periodically after the comparison x update period. It is defined by the CUPR field in the CMPxM. The comparison unit has an update period counter independent from the period counter to trigger this update. When the value of the comparison update period counter CUPRCNT (in CMPxM) reaches the value defined by CUPR, the update is triggered.
PAGE 989
AT32UC3C 33.6.4 PWM Event Lines The PWM provides 2 independent event lines intended to trigger actions in other peripherals (in particular for ADC (Analog to Digital Converter)). A pulse (one cycle of the master clock (CLK_PWM))is generated on an event line, when at least one of the selected comparisons is matching. The comparisons can be selected independently by the CSEL bits in the ”Event Line x Register” on page 1026 (ELxMR for the Event Line x). Figure 33-16.
PAGE 990
AT32UC3C 33.6.5 33.6.5.1 PWM Controller Operations Initialization Before enabling the channels, they must have been configured by the software application: • Unlock user interface by writing the WPCMD field in the WPCR Register. • Configuration of the clock generator (DIVA, PREA, DIVB, PREB, CLKSEL in the CLK register if required). After writing CLKSEL to a new value, no write in any PWM registers must be attempted before a delay of 2 master clock periods (CLK_PWM).
PAGE 991
AT32UC3C 33.6.5.2 Source Clock Selection Criteria The large number of source clocks can make selection difficult. The relationship between the value in the ”Channel Period Register” on page 1040 (CPRDx) and the ”Channel Duty Cycle Register” on page 1038 (CDTYx) can help the user. The event number written in the Period Register gives the PWM accuracy. The Duty-Cycle quantum cannot be lower than 1/CPRDx value. The higher the value of CPRDx, the greater the PWM accuracy.
PAGE 992
AT32UC3C UPR in ”Sync Channels Update Period Register” on page 1009 (SCUP)) and the end of the current PWM period, then updates the value for the next period. 33.6.5.5 Note: If the SCUPUPD update register is written several times between two updates, only the last written value is taken into account. Note: Changing the update period does make sense only if there is one or more synchronous channels and if the update method 1 or 2 is selected (UPDM=1 or 2 in ”Sync Channels Mode Register” on page 1006).
PAGE 993
AT32UC3C 33.6.5.7 Write Protect Registers To prevent any single software error that may corrupt PWM behavior, the registers listed below can be write-protected by writing the WPCMD field in the ”Write Protect Control Register” on page 1028 (WPCR).
PAGE 994
AT32UC3C 33.7 User Interface Table 33-3.
PAGE 995
AT32UC3C Table 33-3.
PAGE 996
AT32UC3C Table 33-3.
PAGE 997
AT32UC3C 33.7.1 Name: Clock Register CLK Access Type: Read/Write Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 CLKSEL - - - 23 22 21 20 27 26 25 24 PREB 19 18 17 16 11 10 9 8 1 0 DIVB 15 14 13 12 - - - - 7 6 5 4 PREA 3 2 DIVA This register can only be written if the WPSWS0 and WPHWS0 bits are cleared in ”Write Protect Status Register” on page 1030. • CLKSEL: CCK Source Clock Selection 0: The PWM internal clock CCK is driven by the master clock CLK_PWM.
PAGE 998
AT32UC3C • PREA, PREB: CLKA, CLKB Source Clock Selection Table 33-4. Source Clock Selection PREA, PREB Divider Input Clock 0 CCK 1 CCK/2 2 CCK/4 3 CCK/8 4 CCK/16 5 CCK/32 6 CCK/64 7 CCK/128 8 CCK/256 9 CCK/512 10 CCK/1024 Other Reserved • DIVA, DIVB: CLKA, CLKB Divide Factor Table 33-5.
PAGE 999
AT32UC3C 33.7.2 Name: Enable Register ENA Access Type: Write-only Offset: 0x004 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – CHID3 CHID2 CHID1 CHID0 • CHIDx: Channel ID Writing a zero to this bit has no effect. Writing a one to this bit will enable the PWM output for channel x.
PAGE 1000
AT32UC3C 33.7.3 Name: Disable Register DIS Access Type: Write-only Offset: 0x008 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – CHID3 CHID2 CHID1 CHID0 This register can only be written if the WPSWS1 and WPHWS1 bits are cleared in ”Write Protect Status Register” on page 1030.
PAGE 1001
AT32UC3C 33.7.4 Name: Status Register SR Access Type: Read-only Offset: 0x00C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – CHID3 CHID2 CHID1 CHID0 • CHIDx: Channel ID 0: PWM output for channel x is disabled. 1: PWM output for channel x is enabled.
PAGE 1002
AT32UC3C 33.7.5 Name: Interrupt Enable Register 1 IER1 Access Type: Write-only Offset: 0x010 Reset Value: - 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – FCHID3 FCHID2 FCHID1 FCHID0 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – CHID3 CHID2 CHID1 CHID0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 1003
AT32UC3C 33.7.6 Name: Interrupt Disable Register 1 IDR1 Access Type: Write-only Offset: 0x014 Reset Value: - 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – FCHID3 FCHID2 FCHID1 FCHID0 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – CHID3 CHID2 CHID1 CHID0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 1004
AT32UC3C 33.7.7 Name: Interrupt Mask Register 1 IMR1 Access Type: Read-only Offset: 0x018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – FCHID3 FCHID2 FCHID1 FCHID0 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – CHID3 CHID2 CHID1 CHID0 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1005
AT32UC3C 33.7.8 Name: Interrupt Status Register 1 ISR1 Access Type: Read-only Offset: 0x01C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – FCHID3 FCHID2 FCHID1 FCHID0 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – CHID3 CHID2 CHID1 CHID0 • FCHIDx: Fault Protection Trigger on Channel x 0: No new trigger of the fault protection since the last read of the ISR1 register.
PAGE 1006
AT32UC3C 33.7.9 Name: Sync Channels Mode Register SCM Access Type: Read/Write Offset: 0x020 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 PTRM - - PTRCS UPDM 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – SYNC3 SYNC2 SYNC1 SYNC0 This register can only be written if the WPSWS2 and WPHWS2 bits are cleared in ”Write Protect Status Register” on page 1030.
PAGE 1007
AT32UC3C • SYNCx: Synchronous Channel x 0: Channel x is not a synchronous channel. 1: Channel x is a synchronous channel.
PAGE 1008
AT32UC3C 33.7.
PAGE 1009
AT32UC3C 33.7.11 Name: Sync Channels Update Period Register SCUP Access Type: Read/Write Offset: 0x02C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 UPRCNT UPR • UPRCNT: Update Period Counter Reports the value of the Update Period Counter.
PAGE 1010
AT32UC3C 33.7.12 Name: Sync Channels Update Period Update Register SCUPUPD Access Type: Write-only Offset: 0x030 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - UPRUPD This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update of synchronous channels.
PAGE 1011
AT32UC3C 33.7.13 Name: Interrupt Enable Register 2 IER2 Access Type: Write-only Offset: 0x034 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0 15 14 13 12 11 10 9 8 CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0 7 6 5 4 3 2 1 0 - - - - UNRE - - WRDY Writing a zero to a bit in this register has no effect.
PAGE 1012
AT32UC3C 33.7.14 Name: Interrupt Disable Register 2 IDR2 Access Type: Write-only Offset: 0x038 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0 15 14 13 12 11 10 9 8 CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0 7 6 5 4 3 2 1 0 - - - - UNRE - - WRDY Writing a zero to a bit in this register has no effect.
PAGE 1013
AT32UC3C 33.7.15 Name: Interrupt Mask Register 2 IMR2 Access Type: Read-only Offset: 0x03C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0 15 14 13 12 11 10 9 8 CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0 7 6 5 4 3 2 1 0 - - - - UNRE - - WRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1014
AT32UC3C 33.7.
PAGE 1015
AT32UC3C 33.7.17 Name: Output Override Value Register OOV Access Type: Read/Write Offset: 0x044 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – OOVL3 OOVL2 OOVL1 OOVL0 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – OOVH3 OOVH2 OOVH1 OOVH0 • OOVLx: Output Override Value for PWML output of the channel x 0: Override value is 0 for PWML output of channel x.
PAGE 1016
AT32UC3C 33.7.18 Name: Output Selection Register OS Access Type: Read/Write Offset: 0x048 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – OSL3 OSL2 OSL1 OSL0 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – OSH3 OSH2 OSH1 OSH0 • OSLx: Output Selection for PWML output of the channel x 0: Dead-time generator output DTOLx selected as PWML output of channel x.
PAGE 1017
AT32UC3C 33.7.19 Name: Output Selection Set Register OSS Access Type: Write-only Offset: 0x04C Reset Value: - 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – OSSL3 OSSL2 OSSL1 OSSL0 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – OSSH3 OSSH2 OSSH1 OSSH0 • OSSLx: Output Selection Set for PWML output of the channel x Writing a zero to this bit has no effect.
PAGE 1018
AT32UC3C 33.7.20 Name: Output Selection Clear Register OSC Access Type: Write-only Offset: 0x050 Reset Value: - 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – OSCL3 OSCL2 OSCL1 OSCL0 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – OSCH3 OSCH2 OSCH1 OSCH0 • OSCLx: Output Selection Clear for PWML output of the channel x Writing a zero to this bit has no effect.
PAGE 1019
AT32UC3C 33.7.21 Name: Output Selection Set Update Register OSSUPD Access Type: Write-only Offset: 0x054 Reset Value: - 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – OSSUPL3 OSSUPL2 OSSUPL1 OSSUPL0 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – OSSUPH3 OSSUPH2 OSSUPH1 OSSUPH0 • OSSUPLx: Output Selection Set for PWML output of the channel x Writing a zero to this bit has no effect.
PAGE 1020
AT32UC3C 33.7.22 Name: Output Selection Clear Update Register OSCUPD Access Type: Write-only Offset: 0x058 Reset Value: - 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – OSCUPL3 OSCUPL2 OSCUPL1 OSCUPL0 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – OSCUPH3 OSCUPH2 OSCUPH1 OSCUPH0 • OSCUPLx: Output Selection Clear for PWML output of the channel x Writing a zero to this bit has no effect.
PAGE 1021
AT32UC3C 33.7.
PAGE 1022
AT32UC3C 33.7.24 Name: Fault Status ReSister FMR Access Type: Read/Write Offset: 0x060 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 7 6 5 4 3 2 1 0 FIV7 FIV6 FIV5 FIV4 FIV3 FIV2 FIV1 FIV0 • FSy: Fault y Status 0: The fault y is not currently active. 1: The fault y is currently active.
PAGE 1023
AT32UC3C 33.7.25 Name: Fault Clear Register FCR Access Type: Write-only Offset: 0x064 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 FCLR7 FCLR6 FCLR5 FCLR4 FCLR3 FCLR2 FCLR1 FCLR0 • FCLRy: Fault y Clear Writing a zero to this bit has no effect.
PAGE 1024
AT32UC3C 33.7.26 Name: Fault Protection Value Register FPV Access Type: Read/Write Offset: 0x068 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – FPVL3 FPVL2 FPVL1 FPVL0 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – FPVH3 FPVH2 FPVH1 FPVH0 This register can only be written if the WPSWS5 and WPHWS5 bits are cleared in ”Write Protect Status Register” on page 1030.
PAGE 1025
AT32UC3C 33.7.27 Name: Fault Protection Enable Register FPE Access Type: Read/Write Offset: 0x06C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FPE3 23 22 21 20 FPE2 15 14 13 12 FPE1 7 6 5 4 FPE0 This register can only be written if the WPSWS5 and WPHWS5 bits are cleared in ”Write Protect Status Register” on page 1030. Only the first 5 bits (number of fault input pins) of FPE0, FPE1, FPE2 and FPE3 are significant.
PAGE 1026
AT32UC3C 33.7.28 Name: Event Line x Register ELxMR Access Type: Read/Write Offset: 0x080 + [x * 0x04] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 CSEL7 CSEL6 CSEL5 CSEL4 CSEL3 CSEL2 CSEL1 CSEL0 • CSELy: Comparison y Selection 0: A pulse is not generated on the event line x when the comparison y matches.
PAGE 1027
AT32UC3C 33.7.29 Name: Stepper Motor Mode Register SMMR Access Type: Read/Write Offset: 0x0B0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - DOWN1 DOWN0 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - GCEN1 GCEN0 • GCENx: Gray Count Enable 0: Disable gray count on PWML[2*x], PWMH[2*x], PWML[2*x+1], PWMH[2*x+1].
PAGE 1028
AT32UC3C 33.7.30 Name: Write Protect Control Register WPCR Access Type: Write-only Offset: 0x0E4 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 WPRG5 WPRG4 WPRG3 WPRG2 WPRG1 WPRG0 WPCMD • WPKEY: Write Protect Key Should be written at value 0x50574D (“PWM” in ASCII). Writing any other value in this field aborts the write operation of the WPCMD field. Always reads as 0.
PAGE 1029
AT32UC3C – ”Channel Period Register” on page 1040 – ”Channel Period Update Register” on page 1042 • Register group 4: – ”Channel Dead Time Register” on page 1045 – ”Channel Dead Time Update Register” on page 1046 • Register group 5: – ”Fault Mode Register” on page 1021 – ”Fault Protection Value Register” on page 1024 – 1029 32117D–AVR-01/12
PAGE 1030
AT32UC3C 33.7.
PAGE 1031
AT32UC3C 33.7.32 Version Register Register Name: VERSION Access Type: Read-only Offset: 0x0FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - 15 14 13 12 11 - - - - 7 6 5 4 MFN 10 9 8 1 0 VERSION 3 2 VERSION • MFN Reserved. No functionality associated. • VERSION Version number of the module. No functionality associated.
PAGE 1032
AT32UC3C 33.7.33 Name: Comparison x Value Register CMPxV Access Type: Read/Write Offset: 0x130 + [x * 0x10] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - CVM 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CV 15 14 13 12 CV 7 6 5 4 CV Only the first 20 bits (channel counter size) of CV field are significant.
PAGE 1033
AT32UC3C 33.7.34 Name: Comparison x Value Update Register CMPxVUPD Access Type: Write-only Offset: 0x134 + [x * 0x10] Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - CVMUPD 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CVUPD 15 14 13 12 CVUPD 7 6 5 4 CVUPD This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match. Only the first 20 bits (channel counter size) of CVUPD field are significant.
PAGE 1034
AT32UC3C 33.7.35 Name: Comparison x Mode Register CMPxM Access Type: Read/Write Offset: 0x138 + [x * 0x10] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 9 8 CUPRCNT 15 14 CUPR 13 12 11 10 CPRCNT 7 6 CPR 5 4 CTR 3 2 1 0 - - - CEN • CUPRCNT: Comparison x Update Period Counter Reports the value of the comparison x update period counter. Note: The CUPRCNT field is read-only.
PAGE 1035
AT32UC3C 33.7.36 Name: PWM Comparison x Mode Update Register CMPxMUPD Access Type: Write-only Offset: 0x13C + [x * 0x10] Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 CTRUPD CUPRUPD 11 10 CPRUPD 3 2 1 0 - - - CENUPD This register acts as a double buffer for the CEN, CTR, CPR and CUPR values. This prevents an unexpected comparison x match.
PAGE 1036
AT32UC3C 33.7.37 Name: Channel Mode Register CMR Access Type: Read/Write Offset: 0x200 + [ch_num * 0x20] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - DTLI DTHI DTE 15 14 13 12 11 10 9 8 - - - - - CES CPOL CALG 7 6 5 4 3 2 1 0 - - - - CPRE This register can only be written if the WPSWS2 and WPHWS2 bits are cleared in ”Write Protect Status Register” on page 1030.
PAGE 1037
AT32UC3C • CPRE: Channel Pre-scaler Table 33-7.
PAGE 1038
AT32UC3C 33.7.38 Name: Channel Duty Cycle Register CDTY Access Type: Read/Write Offset: 0x204 + [ch_num * 0x20] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 20 bits (channel counter size) are significant. • CDTY: Channel Duty-Cycle Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (CPRx).
PAGE 1039
AT32UC3C 33.7.39 Name: Channel Duty Cycle Update Register CDTYUPD Access Type: Write-only Offset: 0x208 + [ch_num * 0x20] Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CDTYUPD 15 14 13 12 CDTYUPD 7 6 5 4 CDTYUPD This register acts as a double buffer for the CDTY value. This prevents an unexpected waveform when modifying the waveform duty-cycle. Only the first 20 bits (channel counter size) are significant.
PAGE 1040
AT32UC3C 33.7.40 Name: Channel Period Register CPRD Access Type: Read/Write Offset: 0x20C + [ch_num * 0x20] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD This register can only be written if the WPSWS3 and WPHWS3 bits are cleared in ”Write Protect Status Register” on page 1030. Only the first 20 bits (channel counter size) are significant.
PAGE 1041
AT32UC3C – By using the PWM internal clock (CCK) divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (--------------------------------------------------2 × CPRD × DIVA )( 2 × CPRD × DIVB ) or ---------------------------------------------------CCK CCK 1041 32117D–AVR-01/12
PAGE 1042
AT32UC3C 33.7.41 Name: Channel Period Update Register CPRDUPD Access Type: Write-only Offset: 0x210 + [ch_num * 0x20] Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CPRDUPD 15 14 13 12 CPRDUPD 7 6 5 4 CPRDUPD This register can only be written if the WPSWS3 and WPHWS3 bits are cleared in ”Write Protect Status Register” on page 1030. This register acts as a double buffer for the CPRD value.
PAGE 1043
AT32UC3C (----------------------------------------------------2 × X × CPRDUPD )CCK – By using the PWM internal clock (CCK) divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (---------------------------------------------------------------2 × CPRDUPD × DIVA )( 2 × CPRDUPD × DIVB ) or ----------------------------------------------------------------CCK CCK 1043 32117D–AVR-01/12
PAGE 1044
AT32UC3C 33.7.42 Name: Channel Counter Register CCNT Access Type: Read-only Offset: 0x214 + [ch_num * 0x20] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CNT 15 14 13 12 CNT 7 6 5 4 CNT Only the first 20 bits (channel counter size) are significant. • CNT: Channel Counter Register Gives the channel counter value.
PAGE 1045
AT32UC3C 33.7.43 Name: Channel Dead Time Register DT Access Type: Read/Write Offset: 0x218 + [ch_num * 0x20] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTL 23 22 21 20 DTL 15 14 13 12 DTH 7 6 5 4 DTH This register can only be written if the WPSWS4 and WPHWS4 bits are cleared in ”Write Protect Status Register” on page 1030. Only the first 16 bits (dead-time counter size) of DTH and DTL fields are significant.
PAGE 1046
AT32UC3C 33.7.44 Name: Channel Dead Time Update Register DTUPD Access Type: Write-only Offset: 0x21C + [ch_num * 0x20] Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTLUPD 23 22 21 20 DTLUPD 15 14 13 12 DTHUPD 7 6 5 4 DTHUPD This register can only be written if the WPSWS4 and WPHWS4 bits are cleared in ”Write Protect Status Register” on page 1030. This register acts as a double buffer for the DTH and DTL values.
PAGE 1047
AT32UC3C 33.8 Module Configuration The specific configuration for each PWM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 33-8. Module name Clock Name Description PWM CLK_PWM Peripheral Bus clock from the PBA clock domain GCLK The generic clock used for the PWM is GCLK4 Table 33-9. 33.8.
PAGE 1048
AT32UC3C 34. Quadrature Decoder (QDEC) Rev.: 1.0.0.0 34.1 Features • Handles three input channels: • • • • • • 34.2 – Two phase signals (QEPA, QEPB) – One index pulse (QEPI) Optional digital filter on inputs 16-bit position counter and 16-bit revolution counter 32-bit timer/counter mode Software trigger or peripheral event trigger Compare function with peripheral event generation Capture function on peripheral event Overview The QDEC is used in rotating motion systems for position and speed detection.
PAGE 1049
AT32UC3C 34.3 Block Diagram Figure 34-2. QDEC Block Diagram compare event CMP register QCF.FILTEN QEPI QEPB Filter QPulse Filter Advanced filter Filter quadrature decoder DIR CNT = position counter/ revolution counter PB QEPA TOP register CLK_QDEC_INT CAP register Clock Control GCLK_QDEC trigger event 34.4 I/O Lines Description Table 34-1. 34.
PAGE 1050
AT32UC3C 34.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the QDEC, the QDEC will stop functioning and resume operation after the system wakes up from sleep mode. 34.5.3 Clocks The QDEC has two clocks connected: One Peripheral Bus clock (CLK_QDEC) and one generic clock (GCLK_QDEC). These clocks are generated by the Power Manager. CLK_QDEC is enabled at reset, and can be disabled in the Power Manager.
PAGE 1051
AT32UC3C Figure 34-3. Clock Control PEVC trigger A N D CTRL[CLKEN]= 1 Set Q CTRL[CLKEN]=0 SR[CLKEN] Reset A N D GCLK_QDEC 34.6.1.2 CLK_QDEC_INT Trigger A trigger resets the QDEC counter and starts CLK_QDEC_INT. Two triggers are possible: • • A software trigger, by writing a one to the Software Trigger bit in CTRL (CTRL.SWTRG). Trigger peripheral event from the PEVC: If enabled by writing a one to the Event Trigger Enable bit in the Configuration Register (CF.EVTRGE).
PAGE 1052
AT32UC3C 34.6.1.4 Position counter The 16-bit position counter is incremented or decremented on every count pulse, generated by the quadrature decoder module. The counting direction is displayed in SR.CNTDIR. If the position counter reaches the TOP.PCTOP value when counting up or the 0 value when counting down, the counter wraps around. The Position Counter Roll Over (PCRO) interrupt is generated. Usually, the TOP.
PAGE 1053
AT32UC3C Figure 34-6. PC reset by QEPI signal (TOP.PCTOP = 79, CF.IDXPHS =”00”, CF.IDXE = “1”) QEPA QEPB QEPI QPulse PC RC 72 73 74 0 75 0 1 2 3 2 1 0 1 79 78 77 0 IDXERR 34.6.1.8 Quadrature frequency The CLK_QDEC clock frequency must be at least two times the QEPA and QEPB frequency as these signals are synchronized to the CLK_QDEC clock. To get the maximum available frequency on QEPA/QEPB signals, the filter on inputs should be bypassed.
PAGE 1054
AT32UC3C 34.6.2.2 Capture register The capture function saves the QDEC counter value in the Capture register (CAP) when a capture event has occurred. The capture function is enabled if the QDEC counter is running. The CAP register will not be updated with a new value if the previous value has not been read. If a capture event occurs and the previous value has not been read, the SR.OVR bit is set. 34.6.2.
PAGE 1055
AT32UC3C Figure 34-7. Timer Block Diagram compare event CMP TOP CF.UPD CF.TSDIR CNT DIR up/down control PB toggle direction event CLK_QDEC_INT CAP Clock Control GCLK_QDEC trigger event capture event The user can set the timer count direction by writing to the CF.TSDIR bit. The counting direction is taken into account when a trigger occurs. The counting direction is shown in SR.CNTDIR. The user has to set the initial direction of counting by writing to CF.TSDIR. When the timer is triggered, i.
PAGE 1056
AT32UC3C • The RCRO interrupt to detect a roll-over of the revolution counter. • The IDXERR interrupt to detect that the index signal (QEPI) is detected and the position counter does not have the expected value (TOP.PCTOP if the counter counts up, 1 if the counter counts down). • The DIRINV interrupt occurs when the count direction changes. • The QDERR interrupt occurs when a bad transition in the quadrature signals is detected (for example, from “00” to “11”).
PAGE 1057
AT32UC3C 34.7 User Interface Table 34-2. 1.
PAGE 1058
AT32UC3C 34.7.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - SWTRG CLKEN • SWTRG: Software Trigger Writing a one to this bit generates a software trigger if CTRL.CLKEN is one. This bit always reads as 0.
PAGE 1059
AT32UC3C 34.7.
PAGE 1060
AT32UC3C • RCCE: Revolution Counter Compare Enable 0: The revolution counter compare is disabled 1: The revolution counter compare is enabled • PCCE: Position Counter Compare Enable 0: The position counter compare is disabled 1: The position counter compare is enabled • IDXE: Index Enable 0: The index signal detection is disabled 1: The index signal detection is enabled • QDEC: QDEC Mode 0: QDEC is in Timer Mode 1: QDEC is in Quadrature Decoder Mode 1060 32117D–AVR-01/12
PAGE 1061
AT32UC3C 34.7.
PAGE 1062
AT32UC3C 34.7.
PAGE 1063
AT32UC3C 34.7.
PAGE 1064
AT32UC3C 34.7.
PAGE 1065
AT32UC3C 34.7.
PAGE 1066
AT32UC3C • CAP: Counter Capture This bit is cleared when the corresponding bit in SCR is written to one This bit is set when a capture event has occurred • CMP: Counter Compare This bit is cleared when the corresponding bit in SCR is written to one This bit is set when compare match occurred • QEPI: Index Signal Detection This bit is cleared when the corresponding bit in SCR is written to one This bit is set when an index detection has occurred 1066 32117D–AVR-01/12
PAGE 1067
AT32UC3C 34.7.8 Status Clear Register Name: SCR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TRIGGER QDERR 7 6 5 4 3 2 1 0 OVR DIRINV IDXERR RCRO PCRO CAP CMP QEPI Writing a zero to a bit in this register has no effect.
PAGE 1068
AT32UC3C 34.7.9 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TRIGGER QDERR 7 6 5 4 3 2 1 0 OVR DIRINV IDXERR RCRO PCRO CAP CMP QEPI 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1069
AT32UC3C 34.7.10 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TRIGGER QDERR 7 6 5 4 3 2 1 0 OVR DIRINV IDXERR RCRO PCRO CAP CMP QEPI Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 1070
AT32UC3C 34.7.11 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TRIGGER QDERR 7 6 5 4 3 2 1 0 OVR DIRINV IDXERR RCRO PCRO CAP CMP QEPI Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 1071
AT32UC3C 34.7.12 Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RCSIZE PCSIZE • RCSIZE: Number of bits -1 in CNT.RC registers • PCSIZE: Number of bits -1 in CNT.
PAGE 1072
AT32UC3C 34.7.13 Version Register Name: VERSION Access Type: Read-only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 9 8 – – – – 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
PAGE 1073
AT32UC3C 34.8 Module Configuration The specific configuration for each QDEC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 34-3.
PAGE 1074
AT32UC3C 35. Analog Comparator Interface (ACIFA) Rev: 1.0.0.1 35.1 Features • Control one set of two analog comparators • High speed option versus low power option • • • • • 35.
PAGE 1075
AT32UC3C 35.3 Block Diagram Figure 35-1. Analog Comparator Interface Overview in normal mode ACIFA CONFA.INSELP ACAOUT SR.ACACS ACxAPi internal inputs EVSRC0.EVSRC] vip A + ACA ACxANi internal inputs vin A acoutA event generator 0 PEVC - Vcc Scale CONFA.INSELN Interrupt Controller interrupt generator CONFA.INSELP ACxBPi internal inputs vip B + Vcc Scale ACB ACxBNi internal inputs vin B - event generator 1 acoutB SR.ACBCS EVSRC1.EVSRC ACBOUT CONFB.INSELN Figure 35-2.
PAGE 1076
AT32UC3C 35.4 I/O Lines Description Table 35-1. Name 35.5 35.5.1 I/O Lines Description Description ACAOUT Analog Comparator A output ACBOUT Analog Comparator B output ACxAPi Positive inputs for comparator ACxA ACxANi Negative inputs for comparator ACxA ACxBPi Positive inputs for comparator ACxB ACxBNi Negative inputs for comparator ACxB Product Dependencies I/O Lines The pins used for interfacing the ACIFA may be multiplexed with the I/O Controller lines.
PAGE 1077
AT32UC3C 35.6.1.1 ACIFA Output An analog comparator generates one output acoutx (with x = a or b) according to the input voltages vipx (AC positive input) and vinx (AC negative input): • acoutx = 1 if vipx > vinx • acoutx = 0 if vipx < vinx • acoutx = 0 if the AC output is not available (ie. The AC Ready bit in the Status Register (SR.
PAGE 1078
AT32UC3C • acwout = 0 if the window mode output is not available (ie. The Window Function Ready bit in the Status Register (SR.
PAGE 1079
AT32UC3C 35.6.6 Input Hysteresis The user can select between no, low, and high hysteresis, by writing in the Hysteresis Selection field in the CONF register (CONFx.HS). Adding hysteresis can avoid constant toggling of the compare output if the input signals are very close to each other. 35.6.7 Startup Time After enabling an Analog Comparator, the comparison is available after a start-up time defined in the Start Up Time field in the Start Up Time register (SUT.SUT).
PAGE 1080
AT32UC3C 35.7 User Interface Table 35-2.
PAGE 1081
AT32UC3C 35.7.
PAGE 1082
AT32UC3C 35.7.
PAGE 1083
AT32UC3C 35.7.
PAGE 1084
AT32UC3C 35.7.4 Name: AC Event 0/1 Configuration Register EVSRC0-EVSRC1 Access Type: Read/Write Offset: 0x0C-0X10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - EVSRC • EVSRC: Event source selection “0000”: The event is set on ACA.acoutA rising edge “0001”: The event is set on ACA.
PAGE 1085
AT32UC3C 35.7.
PAGE 1086
AT32UC3C 35.7.
PAGE 1087
AT32UC3C 35.7.
PAGE 1088
AT32UC3C 35.7.
PAGE 1089
AT32UC3C 35.7.
PAGE 1090
AT32UC3C 35.7.
PAGE 1091
AT32UC3C 35.7.11 Name: AC Interrupt Mask Register IMR Access Type: Read-Only Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - SUTBINT SUTAINT WFINT ACBNT ACAINT 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1092
AT32UC3C 35.7.12 Name: AC Event Enable Register EVE Access Type: Write-Only Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - ACEV1 ACEV0 • ACEV1: Event 1 enable Writing a zero to this bit has no effect Writing a one to this bit will enable the event zero defined in the EVSRC1.
PAGE 1093
AT32UC3C 35.7.13 Name: AC Event Disable Register EVD Access Type: Write-Only Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - ACEV1 ACEV0 • ACEV1: Event 1 enable Writing a zero to this bit has no effect Writing a one to this bit will disable the event one defined in the EVSRC1.
PAGE 1094
AT32UC3C 35.7.
PAGE 1095
AT32UC3C 35.7.
PAGE 1096
AT32UC3C • WFEN: Window function enable This bit is cleared when the window function is disabled This bit is set when the window function is enabled • ACBEN: ACB enable This bit is cleared when the ACB is disabled This bit is set when the ACB is enabled • ACAEN: ACA enable This bit is cleared when the ACA is disabled This bit is set when the ACA is enabled • SUTBINT: ACB startup time interrupt status This bit is cleared when the ACB interrupt is not pending This bit is set when the ACB interrupt is pending
PAGE 1097
AT32UC3C 35.7.16 Name: AC Status Clear Register SCR Access Type: Write-Only Offset: 0x44 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - SUT1INT SUT0INT WFINT ACBNT ACAINT Writing a zero to a bit in this register has no effect.
PAGE 1098
AT32UC3C 35.7.17 Name: Version Register VERSION Access Type: Read-Only Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 1099
AT32UC3C 35.8 Module configuration The specific configuration for each ACIFA instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 35-3. Module clock name Module name Clock name Description ACIFA0 CLK_ACIFA0 Peripheral Bus clock from the PBA clock domain ACIFA1 CLK_ACIFA1 Peripheral Bus clock from the PBA clock domain Table 35-4.
PAGE 1100
AT32UC3C Table 35-7. vin of AC0A selection CONFA[INSELN] Name Connection 0 AC0AN0 1 AC0AN1 See Peripheral Multiplexing on I/O line chapter 2 AC0BP0 3 AC0BP1 4 VVDDANA scaled VVDDANA scaled 5 DAC1_int Internal output of the DAC1 Table 35-8. vip of AC0B selection CONFB[INSELP] Name Connection 0 AC0AN0 1 AC0AN1 See Peripheral Multiplexing on I/O line chapter 2 AC0BP0 3 AC0BP1 4 DAC0_int Internal output of the DAC0 5 VVDDANA scaled VVDDANA scaled Table 35-9.
PAGE 1101
AT32UC3C Table 35-12. vip of AC1B selection CONFB[INSELP] Description Connection 0 AC1AN0 1 AC1AN1 See Peripheral Multiplexing on I/O line chapter 2 AC1BP0 3 AC1BP1 4 DAC0_int Internal output of the DAC0 5 VVDDANA scaled VVDDANA scaled Table 35-13.
PAGE 1102
AT32UC3C 36. ADC Interface (ADCIFA) Rev. 1.1.0.4 36.1 Features • 8/10/12-bit ADC core with built-in dual sample and hold (S/H) • 16 channels • Up to 1.5 mega-samples per second conversion rate for 12 bits resolution – Conversion time near to 5.3µs (12 bits resolution at 1.5 Msps) • Up to 2 mega-samples per second conversion for lower resolution • • • • • • • • • • • • • – Conversion time near to 3.
PAGE 1103
AT32UC3C 36.2 Overview The Analog-to-Digital Converter (ADC) is fully differential and based on a 12-bit pipelined topology using switched capacitors circuitry. Two sample and hold (S/H) running simultaneously with 1, 2, 4, 8, 16, 32, 64 gain factors are feeding a single ADC analog block so that the system acts as if there were two conversion running in parallel. It can be configured as a 8-bit 10-bit or 12-bit ADC and is capable of converting 1.5 million samples per second thanks to its pipeline topology.
PAGE 1104
AT32UC3C 36.3 Block Diagram Figure 36-1. ADCIFA Block Diagram PB PDC ADC result0 ADC Window0 RES0 . . . RES7 GNDANA PDC ADC Window1 VDDANA ADC result1 RES8 . . .
PAGE 1105
AT32UC3C 36.4 I/O Lines Description Table 36-1. 36.5 36.5.1 I/O Lines Description Name Description ADCINx ADC analog input ADCREFP CFG.EXREF= 0: Normal operation, this pin is used to decouple ADC internal reference. ADCREFP should be connected to a 100nF external decoupling capacitor. CFG.EXREF= 1: Forcing reference using ADCREFP/ADCREFN differential pin pair voltage Please refer to the Section 36.6.10 for more information. ADCREFN CFG.
PAGE 1106
AT32UC3C 36.5.6 Debug Operation When an external debugger forces the CPU into debug mode: • the ADCIFA continues normal operation if the bit related to ADCIFA in PDBG register is ‘0’. PDCA access continues normal operation and may interfere with debug operation. • the ADCIFA is frozen if the bit related to ADCIFA in PDBG register is ‘1’. When the ADCIFA is frozen, ADCIFA PB registers can still be accessed. Then, reading registers may modify status bits (OVRx, LOVRx) like in normal operation.
PAGE 1107
AT32UC3C 36.6.3 Power Reduction Modes Configuration bits acting on the power consumption of the digital and analog blocks are ADC enable (ADCEN) and Sleep Mode Selection (SLEEP) bits located in the CFG register: Table 36-3.
PAGE 1108
AT32UC3C Figure 36-2. Single Sequencer Chronogram (assuming SRES=8, SHD=0) 36.6.4.3 Dual-sequencer mode (simultaneous sampling) The ADC has the ability to sample two pairs of ADCINx inputs simultaneously (see Figure 36-3), provided that one pair is from the inputs available on the sequencer 0 and the other is from the inputs available on the sequencer 1 (see Figure 36-1). To put the ADC into simultaneous sampling mode, the SSMQ bit needs to be clear in the CFG register. Figure 36-3.
PAGE 1109
AT32UC3C 36.6.4.5 Sequencer start/stop mode Thanks to the Software Acknowledge bit (SA) in the SEQCFGx register, the behavior of sequencer x at the end of a sequence can be configured. Table 36-6. SA Sequencer Start/Stop Mode Comment 0 The sequencer waits for software acknowledge. Acknowledge is done by writing a 1 in the SEOSx bit of the SCR register. 1 The sequencer will restart automatically a new sequence on a new SOC. Results will be overwritten if not processed.
PAGE 1110
AT32UC3C Figure 36-5. Using FRM and Converting at Full Speed 36.6.5 ADC Clock Configuration (CKDIV) The clock frequency range for the ADC is [1.5 MHz - 32 KHz]. Since the ADC interface uses the system clock up to the PB maximum frequency, a clock downscale must be done if a higher frequency system clock is used. This scaling may also be done in order to slow down the ADC conversions or increase the S/H time, without affecting the system clock.
PAGE 1111
AT32UC3C Figure 36-7. Multiplexers Settle Time Depending on the CFG.MUXSET Configuration Bit The chronogram above shows that for the same start of conversion (SOC) event, CkADC rises one PB clock period later. The ADC and S/H are sampling when CkADC is high, so setting the CFG.MUXSET bit will delay the sampling phase by one PB clock period. 36.6.7 Oversampling Mode To improve conversion accuracy, it is recommended to perform oversampling. This is particularly useful for high impedance sources.
PAGE 1112
AT32UC3C 36.6.8 Sample & Hold (S/H) with Gain The ADC preamplifiers are made of two cascaded switched-capacitors amplifiers stages. They are used to sample analog voltages and provide it to the ADC block when it has a time slot to make the conversion. It also amplifies the input voltage.
PAGE 1113
AT32UC3C 36.6.8.1 Dynamic mode Dynamic mode aims at improving conversion accuracy when performing channel sweeping or measures on high frequency input signals. It is then recommended using the SHDYN (sample and hold dynamic mode) bit control in the SEQCFGx register. Doing this causes the insertion of a supplementary sampling cycle of one CkADC clock period used to reset the sample and hold. As a consequence, conversion rate is divided by two.
PAGE 1114
AT32UC3C 36.6.9 Power-up and Startup Time To convert correct values, both references and ADC have to be powered-up correctly, otherwise wrong values will be converted until the end of the start-up time. • Cold start-up: References needs 1 ms max to establish. • Hot start-up: Once references are up, 24 CkADC clock periods are needed. When in sleep mode, the HOT start-up sequence is performed each time a conversion or a sequence is triggered thanks to the SOCB bit in the SEQCFGx register.
PAGE 1115
AT32UC3C 36.6.10 Analog Reference The following sources are available as analog reference (AREF) in the ADC. They are selected through the Reference Source (RS) field in the CFG register: • 1V internal voltage reference • 0.6*VDDANA internal voltage reference • Two external reference voltage (ADCREF0 or ADCREF1 over chip analog ground) When using an internal reference, it is recommended inserting a decoupling capacitor between ADCREFP and ADCREFN externally (mandatory to get the full 12-bits precision).
PAGE 1116
AT32UC3C 36.6.13 Start Of Conversion (SOC) ADC sequencers conversions can be triggered for each sequencer with the following sources: Table 36-9. Trigger of Start Of Conversion Source Sequencer Software trigger Internal Timer Event controller Continuous SEQ0 Y Y Y Y SEQ1 Y Y Y Y The sources must be configured through the Trigger Selection (TRGSEL) field of the SEQCFGxregister.
PAGE 1117
AT32UC3C 36.6.16 Calibration Accuracy of the conversion is based on calibration of switched capacitors and operational amplifiers offset cancellation. Gain correction is done by writing a calibration word into the ADCCAL and SHCAL registers since it is temperature and operating voltage independent. 36.6.16.
PAGE 1118
AT32UC3C 36.6.18 Arbitration In dual sequencer mode, SEQ0 has priority over SEQ 1. Due to the ADC pipeline topology, the arbiter is implemented in order to allocate optimal time slots to each sequencer in order to pipe requests. When all analog voltages have been taken into account in the ADC pipeline, an other sequencer can drive the analog blocs without waiting for the end of the whole conversion process. The ADC result will be sampled by another process when getting the wanted precision. 36.6.
PAGE 1119
AT32UC3C 36.7 User Interface Table 36-12.
PAGE 1120
AT32UC3C 36.7.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - TSTART TSTOP SOC1 SOC0 • TSTART: Internal Timer Start Bit Writing a zero to this bit has no effect. Writing a one to this bit starts the internal timer. This bit always reads as zero.
PAGE 1121
AT32UC3C 36.7.2 Name: Configuration Register CFG Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - 15 14 13 12 11 10 9 8 - - - - - MUXSET EXREF - 7 6 5 4 3 2 1 0 FRM SSMQ SLEEP - ADCEN SHD SUT RS It is adviced not changing the configuration once the module is enabled. In order to do so, first turn off the module by writting a 0 in CFG.
PAGE 1122
AT32UC3C 1: The free running mode is enabled, sequencer 0 performs conversions continuously. 0: The free running modeis disabled. note: once in this mode, sequencer 1 requests cannot be serviced. • SSMQ: Single Sequencer Mode 1: The single sequencer mode is enabled, sequencers 0 and 1 are merged, increasing the number of conversions per sequence. 0: The single sequencer mode is disabled, SEQ0 and SEQ1 are in simultaneous mode. • SLEEP: Sleep Mode Selection 1: The power saving mode is enabled.
PAGE 1123
AT32UC3C 36.7.3 Name: Status Register SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 - - - - 23 22 21 20 - - - 15 14 13 12 11 RUNT SUTD MSOC1 MSOC0 7 6 5 LOVR1 OVR1 SEOC1 26 25 24 17 16 10 9 8 WM1 WM0 - - 4 3 2 1 0 SEOS1 LOVR0 OVR0 SEOC0 SEOS0 STATE1 19 18 STATE0 • STATE1: Sequencer 1 State Register This field is set to the current conversion identifier.
PAGE 1124
AT32UC3C • WM0: Window Monitor 0 This bit is set when the watched result value goes to the defined window. This bit is cleared when the corresponding bit in SCR is written to one. • LOVR1: Sequencer 1 Last Converted Value Overrun This bit is set when an overrun error occurs on the LCV register. This bit is cleared when the corresponding bit in SCR is written to one. • OVR1: Sequencer 1 Overrun Error This bit is set when an overrun error occurs.
PAGE 1125
AT32UC3C 36.7.4 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - SUTD MSOC1 MSOC0 WM1 WM0 - - 7 6 5 4 3 2 1 0 LOVR1 OVR1 SEOC1 SEOS1 LOVR0 OVR0 SEOC0 SEOS0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register clears the corresponding bit in SR.
PAGE 1126
AT32UC3C 36.7.5 Name: Status Set Register SSR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - SUTD MSOC1 MSOC0 WM1 WM0 - - 7 6 5 4 3 2 1 0 LOVR1 OVR1 SEOC1 SEOS1 LOVR0 OVR0 SEOC0 SEOS0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register sets the corresponding bit in SR.
PAGE 1127
AT32UC3C 36.7.6 Name: Sequencer n Configuration Register SEQCFGn Access Type: Read/Write Offset: 0x14 + n * 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 9 8 - - 7 6 5 - - - CNVNB 12 11 10 - - 4 3 2 1 0 SHDYN OVSX2 SOCB HWLA SA SRES TRGSEL It is adviced not changing the configuration once the module is enabled. In order to do so, first turn off the module by writting a 0 in CFG.
PAGE 1128
AT32UC3C 1: The SOCB mode is enabled, a single conversion is performed on a SOC event. 0: The SOCB mode is disabled, a complete sequence is performed on a SOC event. • HWLA: Half Word Left Adjust 1: The HWLA mode is enabled. 0: The HWLA mode is disabled. • SA: Software Acknowledge 1: The SA mode is enabled. 0: The SA mode is disabled.
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AT32UC3C 36.7.
PAGE 1130
AT32UC3C 36.7.
PAGE 1131
AT32UC3C 36.7.
PAGE 1132
AT32UC3C 36.7.
PAGE 1133
AT32UC3C 36.7.
PAGE 1134
AT32UC3C 36.7.12 Name: Clock Divider Register CKDIV Access Type: Read/Write Offset: 0x44 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - CNT[8] 7 6 5 4 3 2 1 0 CNT[7:0] • CNT: Max Counter Value Number of ADC clock cycles to count: (CNT + 1) * 2.
PAGE 1135
AT32UC3C 36.7.13 Name: Internal Timer Register ITIMER Access Type: Read/Write Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - ITMC[16] 15 14 13 12 11 10 9 8 3 2 1 0 ITMC[15:8] 7 6 5 4 ITMC[7:0] • ITMC: Internal Timer Max Counter Number of ADC clock cycles to wait for is (ITMC + 1). note: This allows SOC period up to 167 ms when CkADC clock is running at 1.5 MHz.
PAGE 1136
AT32UC3C 36.7.14 Name: Window Monitor n Configuration Register WCFGn Access Type: Read/Write Offset: 0x58+ n * 0x04 Reset Value: 0x00000000 31 30 29 - 28 27 26 25 SRC 23 22 21 24 WM 20 19 18 17 16 11 10 9 8 1 0 HT[11:4] 15 14 13 12 HT[3:0] 7 6 LT[11:8] 5 4 3 2 LT[7:0] • SRC: Index of the result register to monitor (0 to 16). • WM: Window Mode 0: No window mode. 1: Mode 1: RES(SRC) < HT. 2: Mode 2: RES(SRC) > LT. 3: Mode 3: LT< RES(SRC) < HT.
PAGE 1137
AT32UC3C 36.7.15 Name: Sequencer n Last Converted Value LCVn Access Type: Read-only Offset: 0x60+ n * 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 LCV[31:24] 23 22 21 20 LCV[23:16] 15 14 13 12 LCV[15:8] 7 6 5 4 LCV[7:0] • LCV: Last Converted Value This field is set by hardware to the last sequencer converted value. Depending on precision, the higher bits are padded with the sign bit.
PAGE 1138
AT32UC3C 36.7.
PAGE 1139
AT32UC3C 36.7.
PAGE 1140
AT32UC3C 36.7.18 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x70 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - SUTD MSOC1 MSOC0 WM1 WM0 - - 7 6 5 4 3 2 1 0 LOVR1 OVR1 SEOC1 SEOS1 LOVR0 OVR0 SEOC0 SEOS0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 1141
AT32UC3C 36.7.19 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x74 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - SUTD MSOC1 MSOC0 WM1 WM0 - - 7 6 5 4 3 2 1 0 LOVR1 OVR1 SEOC1 SEOS1 LOVR0 OVR0 SEOC0 SEOS0 Writing a zero to a bit in this register has no effect.
PAGE 1142
AT32UC3C 36.7.20 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x78 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - SUTD MSOC1 MSOC0 WM1 WM0 - - 7 6 5 4 3 2 1 0 LOVR1 OVR1 SEOC1 SEOS1 LOVR0 OVR0 SEOC0 SEOS0 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1143
AT32UC3C 36.7.21 Name: Version Register VERSION Access Type: Read-only Offset: 0x7C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 1144
AT32UC3C 36.7.
PAGE 1145
AT32UC3C 36.7.23 Name: Result Register RESn Access Type: Read-only Offset: 0x84+ n * 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RES[31:24] 23 22 21 20 RES[23:16] 15 14 13 12 RES[15:8] 7 6 5 4 RES[7:0] • RES: Result register Contains value of conversion n.
PAGE 1146
AT32UC3C 36.8 Module configuration The specific configuration for each ADC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 36-13. Module configuration Feature ADCIFA NBCONV 8 Table 36-14. Module clock name Module name Clock name Description ADCIFA CLK_ADCIFA Peripheral Bus clock from the PBC clock domain Table 36-15.
PAGE 1147
AT32UC3C The following table defines the valid settings for the CONV field of the INPSELxy and INNSELxy registers in the ADCIFA. This setting defines the mapping of the ADC input voltage. Table 36-16.
PAGE 1148
AT32UC3C 37. DACIFB Interface (DACIFB) Rev.: 1.1.0.1 37.1 Features • • • • • • • • 37.
PAGE 1149
AT32UC3C 37.3 Block Diagram Figure 37-1.
PAGE 1150
AT32UC3C 37.4 I/O Lines Description Table 37-1. 37.5 37.5.1 I/O Lines Description Pin Name Pin Description Type Active Level DACA DAC channel A analog output Output N/A DACB DAC channel B analog output Output N/A DACREF DAC voltage reference Input N/A Product Dependencies I/O Lines The pins used for interfacing the DAC may be multiplexed with GPIO lines. The programmer must first program the GPIO controller to assign the desired DAC pins to their peripheral function.
PAGE 1151
AT32UC3C 37.6 Functional Description 37.6.1 37.6.1.1 Basic Operation Output channels The output from the DAC can either be continuous to one pin (DAC channel A only), or fed to two different pins using a sample and hold circuitry (S/H). With S/H these two outputs can act independently and create two different analog signals, different in both voltage and frequency. The two S/H outputs have individual data and conversion control registers.
PAGE 1152
AT32UC3C 37.6.1.4 Data Registers Data to be converted is taken from two registers, one for each channel: Data Register 0 (DR0) for channel A and Data Register 1 (DR1) for channel B. Alternatively both samples to be converted can be written to DR0 in a single write cycle, in this configuration the values for channel B and A are written to the upper and the lower half words of DR0, respectively. This operation is possible only if the DAC Dual Data in Data Register A bit of the Configuration register (CFR.
PAGE 1153
AT32UC3C Figure 37-2. DAC Timing Counters Channel Interval Counter TCR.CHI[6:0] Prescaler Refresh Counter PrescalerClock TCR.PRESC[2:0] TCR.CHRA[3:0] CLK_DACIFB Refresh Counter TCR.CHRB[3:0] 37.6.2.2 Timing Counter Timing Counter TRA.TCD[7:0] TRB.TCD[7:0] Low Power mode In order to reduce the power consumption during DAC conversions, the DAC Low Power mode may be enabled. In low power mode, the DAC is turned off between each conversion.
PAGE 1154
AT32UC3C VDACxX = gain x (DATACHx / 0xFFF) + offset In an ideal DAC, gain is 1 and offset 0. 37.6.3 Interrupts An interrupt request will be generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR).
PAGE 1155
AT32UC3C 37.7 User Interface Table 37-2. 1.
PAGE 1156
AT32UC3C 37.7.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - ARBE ARAE TRBE TRAE 23 22 21 20 19 18 17 16 - - - - - - BOE AOE 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - EN • ARBE: DAC Auto Refresh Channel B Enable 0: auto-refresh on channel B is disabled. 1: auto-refresh on channel B is enabled.
PAGE 1157
AT32UC3C 37.7.2 Name: Configuration Register CFR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - 23 22 21 20 19 18 17 16 - - - - - - ABE AAE 15 14 13 12 11 10 9 8 - - - - - - - REF 7 6 5 4 3 2 1 0 - - - - - DSE DDA LP CHC • CHC: DAC Channel Configuration These bits control whether the DAC should operate with sample and hold on outputs or not.
PAGE 1158
AT32UC3C • DSE: DAC Data Setup Extra Clock Cycle 0: No extra clock latency. 1: Add an extra clock cycle latency between data written and start of conversion. This may be useful when the DAC clock is running fast. Adding an extra clock cycle latency might help meeting the data setup time constraint. • DDA: DAC Dual Data in Data Register A 0:No dual data in DR0. 1:Dual data in DR0. This allows writing two 16-bit wide data words in a single write operation to the DR0 register.
PAGE 1159
AT32UC3C 37.7.
PAGE 1160
AT32UC3C 37.7.4 Name: Timing Control Register TCR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 - - - - - 23 22 21 20 19 - 26 25 24 PRESC 18 17 16 10 9 8 1 0 CHI 15 14 13 12 - - - - 7 6 5 4 - - - - 11 CHRB 3 2 CHRA • PRESC: DAC Timer Prescaler The prescaling ratio between PrescalerClock and CLK_DACIFB.
PAGE 1161
AT32UC3C • CHRn : DAC Channel Refresh Timing Control Channel n The time interval between each channel output refresh. This interval avoids losing accuracy of the converted value between two consecutive conversions when the sampling rate is low.
PAGE 1162
AT32UC3C 37.7.5 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - DEB DEA 15 14 13 12 11 10 9 8 - - - - - - UA UA 7 6 5 4 3 2 1 0 - - - - - - OB OA Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 1163
AT32UC3C 37.7.6 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - DEB DEA 15 14 13 12 11 10 9 8 - - - - - - UB UA 7 6 5 4 3 2 1 0 - - - - - - OB OA Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 1164
AT32UC3C 37.7.7 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - DEB DEA 15 14 13 12 11 10 9 8 - - - - - - UB UA 7 6 5 4 3 2 1 0 - - - - - - OB OA 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1165
AT32UC3C 37.7.8 Name: Status Register SR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - DEB DEA 15 14 13 12 11 10 9 8 - - - - - - UB UA 7 6 5 4 3 2 1 0 - - - - - - OB OA • DEB: DAC Data Register Empty Channel B Flag 0: Data register not empty, writing to the data register may cause losing a conversion value.
PAGE 1166
AT32UC3C 37.7.9 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - DEB DEA 15 14 13 12 11 10 9 8 - - - - - - UB UA 7 6 5 4 3 2 1 0 - - - - - - OB OA Writing a bit to one will clear the corresponding bit in ISR. Writing a bit to zero has no effect.
PAGE 1167
AT32UC3C 37.7.10 Name: Data Register Control Channel A DRCA Access Type: Read/Write Offset: 0x24 Reset Value: 0x00000001 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - DSD 7 6 5 4 3 2 1 0 - - - - - - - DRN DSV • DSD: DAC Data Shift Direction 0: DAC input value to be converted is right aligned 1: DAC input value to be converted is left aligned.
PAGE 1168
AT32UC3C 37.7.11 Name: Data Register Control Channel B DRCB Access Type: Read/Write Offset: 0x28 Reset Value: 0x00000001 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - DSD 7 6 5 4 3 2 1 0 - - - - - - - DRN DSV • DSD: DAC Data Shift Direction 0: DAC input value to be converted is right aligned 1: DAC input value to be converted is left aligned.
PAGE 1169
AT32UC3C 37.7.12 Name: Data Register Channel 0 DR0 Access Type: Read/Write Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DCB 23 22 21 20 DCB 15 14 13 12 DCA 7 6 5 4 DCA • DCB: DAC Data Channel B The right-aligned 12-bit value to be converted on channel B, when the DDA bit within the CFR register is activated. This allows conversions on both channels in a single register write cycle.
PAGE 1170
AT32UC3C 37.7.13 Name: Data Register Channel 1 DR1 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 DCB 7 6 5 4 DCB • DCB: DAC Data Channel B The right-aligned 12-bit value to be converted on channel B.
PAGE 1171
AT32UC3C 37.7.14 Name: Gain and Offset Calibration Register GOC Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 GCR 23 22 21 20 GCR 15 14 13 12 OCR 7 6 5 4 OCR • GCR: DAC Gain Calibration Value These bits are used to compensate the gain error in the DAC. The MSB is the sign bit. Note that the size of the GCR field can change depending of implementation. See the Module Configuration section.
PAGE 1172
AT32UC3C 37.7.15 Name: Timer Register Channel A TRA Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 TRL - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TCD • TRL: DAC Timer Reload Write this bit to one to re-initialize the counter. • TCD: DAC Timer Count Down Value These bits are used to program the timing counter countdown value.
PAGE 1173
AT32UC3C 37.7.16 Name: Timer Register Channel B TRB Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 TRL - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TCD • TRL: DAC Timer Reload Write this bit to one to re-initialize the counter. • TCD: DAC Timer Count Down Value These bits are used to program the timing counter countdown value.
PAGE 1174
AT32UC3C 37.7.17 Name: Version Register VERSION Access Type: Read-only Offset: 0x40 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION 3 2 VERSION • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 1175
AT32UC3C 37.8 Module Configuration The specific configuration for each DACIFB instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 37-3. DACIFB Configuration Feature DACIFB0 DACIFB1 GOC.GCR size 8-bit 8-bit GOC.OCR size 9-bit 9-bit Table 37-4.
PAGE 1176
AT32UC3C 38. aWire UART (AW) Rev: 2.3.0.0 38.1 Features • Asynchronous receiver or transmitter when the aWire system is not used for debugging. • One- or two-pin operation supported. 38.2 Overview If the AW is not used for debugging, the aWire UART can be used by the user to send or receive data with one start bit, eight data bits, no parity bits, and one stop bit. This can be controlled through the aWire UART user interface. This chapter only describes the aWire UART user interface.
PAGE 1177
AT32UC3C 38.4 I/O Lines Description Table 38-1. I/O Lines Description Name Description Type DATA aWire data multiplexed with the RESET_N pin. Input/Output 38.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 38.5.1 I/O Lines The pin used by AW is multiplexed with the RESET_N pin. The reset functionality is the default function of this pin.
PAGE 1178
AT32UC3C 38.6.1 How to Initialize The Module To initialize the aWire UART user interface the user must first enable the clock by writing a one to the Clock Enable bit in the Clock Request Register (CLKR.CLKEN) and wait for the Clock Enable bit in the Status Register (SR.CENABLED) to be set. After doing this either receive, transmit or receive with resync must be selected by writing the corresponding value into the Mode field of the Control (CTRL.MODE) Register.
PAGE 1179
AT32UC3C 38.6.6 Interrupts To make the CPU able to do other things while waiting for the aWire UART user interface to finish its operations the aWire UART user interface supports generating interrupts. All status bits in the Status Register can be used as interrupt sources, except the SR.BUSY and SR.CENABLED bits. To enable an interrupt the user must write a one to the corresponding bit in the Interrupt Enable Register (IER).
PAGE 1180
AT32UC3C 38.7 User Interface Table 38-2.
PAGE 1181
AT32UC3C 38.7.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - MODE • MODE: aWire UART user interface mode Table 38-3. aWire UART user interface Modes MODE Mode Description 0 Disabled 1 Receive 2 Transmit 3 Receive with resync.
PAGE 1182
AT32UC3C 38.7.2 Name: Status Register SR Access Type: Read-only Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - CENABLED - BUSY • TRMIS: Transmit Mismatch 0: No transfers mismatches. 1: The transceiver was active when receiving.
PAGE 1183
AT32UC3C This bit is set when the clock is disabled. This bit is cleared when the clock is enabled. • BUSY: Synchronizer Busy 0: The asynchronous interface is ready to accept more data. 1: The asynchronous interface is busy and will block writes to CTRL, BRR, and THR. This bit is set when the asynchronous interface becomes busy. This bit is cleared when the asynchronous interface becomes ready.
PAGE 1184
AT32UC3C 38.7.3 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect.
PAGE 1185
AT32UC3C 38.7.4 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 1186
AT32UC3C 38.7.5 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 1187
AT32UC3C 38.7.6 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - - - - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1188
AT32UC3C 38.7.7 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data The last byte received.
PAGE 1189
AT32UC3C 38.7.8 Name: Transmit Holding Register THR Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Transmit Data The data to send.
PAGE 1190
AT32UC3C 38.7.9 Name: Baud Rate Register BRR Access Type: Read/Write Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 BR[15:8] 7 6 5 4 BR[7:0] • BR: Baud Rate The baud rate ( f br ) of the transmission, calculated using the following formula ( f aw is the RC120M frequency): 8f aw f br = ---------BR BR should not be set to a value smaller than 32.
PAGE 1191
AT32UC3C 38.7.10 Name: Version Register VERSION Access Type: Read-only Offset: 0x24 Reset Value: 0x00000200 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 1192
AT32UC3C 38.7.11 Name: Clock Request Register CLKR Access Type: Read/Write Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - CLKEN • CLKEN: Clock Enable 0: The aWire clock is disabled. 1: The aWire clock is enabled. Writing a zero to this bit will disable the aWire clock.
PAGE 1193
AT32UC3C 38.8 Module Configuration The specific configuration for each aWire instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 38-4. Module clock name Module name Clock name Description aWire CLK_AW Peripheral Bus clock from the PBA clock domain Table 38-5.
PAGE 1194
AT32UC3C 39. Programming and Debugging 39.1 Overview The AT32UC3C supports programming and debugging through two interfaces, JTAG or aWire™. JTAG is an industry standard interface and allows boundary scan for PCB testing, as well as daisy-chaining of multiple devices on the PCB. aWire is an Atmel proprietary protocol which offers higher throughput and robust communication, and does not require application pins to be reserved.
PAGE 1195
AT32UC3C Table 39-1. 39.2.2 39.2.2.1 SAB Slaves, addresses and descriptions. Slave Address [35:32] Description HSB 0x5 Alternative mapping for HSB space, for compatibility with other 32-bit AVR devices. Memory Service Unit 0x6 Memory Service Unit registers Reserved Other Unused SAB security restrictions The Service Access bus can be restricted by internal security measures. A short description of the security measures are found in the table below.
PAGE 1196
AT32UC3C Table 39-4.
PAGE 1197
AT32UC3C 39.3 On-Chip Debug Rev: 2.0.0.0 39.3.1 Features • • • • • • • • 39.3.2 Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.
PAGE 1198
AT32UC3C selectable by OCD Registers, minimizing the chance that the AUX port will need to be shared with an application. Table 39-5. 39.3.
PAGE 1199
AT32UC3C 39.3.5 Block Diagram Figure 39-1. On-Chip Debug Block Diagram aWire JTAG aWire JTAG AUX On-Chip Debug Memory Service Unit Service Access Bus Transmit Queue Watchpoints Debug PC Debug Instruction Breakpoints CPU 39.3.6 Program Trace Internal SRAM HSB Bus Matrix Data Trace Ownership Trace Memories and peripherals SAB-based Debug Features A debugger can control all OCD features by writing OCD registers over the SAB interface.
PAGE 1200
AT32UC3C Figure 39-2. JTAG-based Debugger PC JTAG -based debug tool 10-pin ID C JTAG 32-bit AVR Figure 39-3. aWire-based Debugger PC aWire-based debug tool aWire 32-bit AVR 39.3.6.1 Debug Communication Channel The Debug Communication Channel (DCC) consists of a pair OCD registers with associated handshake logic, accessible to both CPU and debugger. The registers can be used to exchange data between the CPU and the debugmaster, both runtime as well as in debug mode.
PAGE 1201
AT32UC3C The OCD system can generate an interrupt to the CPU when DCCPU is read and when DCEMU is written. This enables the user to build a custum debug protocol using only these registers. The DCCPU and DCEMU registers are available even when the security bit in the flash is active. For more information refer to the AVR32UC Technical Reference Manual. 39.3.6.2 Breakpoints One of the most fundamental debug features is the ability to halt the CPU, to examine registers and the state of the system.
PAGE 1202
AT32UC3C 39.3.7.1 Cyclic Redundancy Check (CRC) The MSU can be used to automatically calculate the CRC of a block of data in memory. The MSU will then read out each word in the specified memory block and report the CRC32-value in an MSU register. 39.3.7.2 NanoTrace The MSU additionally supports NanoTrace. This is a 32-bit AVR-specific feature, in which trace data is output to memory instead of the AUX port.
PAGE 1203
AT32UC3C Figure 39-4. AUX+JTAG Based Debugger PC T ra c e b u ffe r A U X +JTA G d e b u g to o l M ic to r 3 8 AUX h ig h s p e e d JTA G AVR 32 39.3.8.1 Trace Operation Trace features are enabled by writing OCD registers by the debugger. The OCD extracts the trace information from the CPU, compresses this information and formats it into variable-length messages according to the Nexus standard.
PAGE 1204
AT32UC3C which are controlled by a pair of OCD registers which determine the range of addresses (or single address) which should produce data trace messages. 39.3.8.4 Ownership Trace Program and data trace operate on virtual addresses. In cases where an operating system runs several processes in overlapping virtual memory segments, the Ownership Trace feature can be used to identify the process switch.
PAGE 1205
AT32UC3C 39.4 JTAG and Boundary-scan (JTAG) Rev: 2.3.0.4 39.4.1 Features • IEEE1149.1 compliant JTAG Interface • Boundary-scan Chain for board-level testing • Direct memory access and programming capabilities through JTAG Interface 39.4.2 Overview The JTAG Interface offers a four pin programming and debug solution, including boundary-scan support for board-level testing. Figure 39-5 on page 1206 shows how the JTAG is connected in an 32-bit AVR device.
PAGE 1206
AT32UC3C 39.4.3 Block Diagram Figure 39-5. JTAG and Boundary-scan Access 32-bit AVR device JTAG JTAG master Boundary scan enable TAP Controller TDO TDI JTAG Pins TMS TCK TCK TMS TDI TDO Instruction register scan enable Data register scan enable Instruction Register TMS TCK TDO TDI JTAG data registers 2nd JTAG device Device Identification Register Boundary Scan Chain Pins and analog blocks By-pass Register Reset Register Part specific registers ... Service Access Bus interface SAB 39.
PAGE 1207
AT32UC3C 39.4.5.1 I/O Lines The TMS, TDI, TDO, and TCK pins are multiplexed with I/O lines. When the JTAG is used the associated pins must be enabled. To enable the JTAG pins, refer to Section 39.4.7. While using the multiplexed JTAG lines all normal peripheral activity on these lines is disabled. The user must make sure that no external peripheral is blocking the JTAG lines while debugging. 39.4.5.
PAGE 1208
AT32UC3C Figure 39-6.
PAGE 1209
AT32UC3C 39.4.7 How to Initialize the Module To enable the JTAG pins the TCK pin must be held low while the RESET_N pin is released. After enabling the JTAG interface the halt bit is set automatically to prevent the system from running code after the interface is enabled. To make the CPU run again set halt to zero using the HALT command.. JTAG operation when RESET_N is pulled low is not possible.
PAGE 1210
AT32UC3C of TCK. In order to remain in the Shift-DR state, the TMS input must be held low. While the Data Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the TDO pin. Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state.
PAGE 1211
AT32UC3C which is linked to the JTAG through a bus master module, which also handles synchronization between the TCK and SAB clocks. For more information about the SAB and a list of SAB slaves see the Service Access Bus chapter. 39.4.11.1 SAB Address Mode The MEMORY_SIZED_ACCESS instruction allows a sized read or write to any 36-bit address on the bus.
PAGE 1212
AT32UC3C continue shifting the same instruction until the busy bit clears, or start shifting data. If shifting data, you must be prepared that the data shift may also report busy. • During Shift-DR of an address: The new address is ignored. The SAB stays in address mode, so no data must be shifted. Repeat the address until the busy bit clears. • During Shift-DR of read data: The read data is invalid. The SAB stays in data mode. Repeat scanning until the busy bit clears.
PAGE 1213
AT32UC3C • Perform a CHIP_ERASE to clear the security bit. NOTE: This will erase all the contents of the non-volatile memory. 39.5 JTAG Instruction Summary The implemented JTAG instructions in the 32-bit AVR are shown in the table below. Table 39-7. Instruction OPCODE JTAG Instruction Summary Instruction Description 0x01 IDCODE Select the 32-bit Device Identification register as data register. 0x02 SAMPLE_PRELOAD Take a snapshot of external pin values without affecting system operation.
PAGE 1214
AT32UC3C Note that the security bit will read as programmed and block these instructions also if the Flash Controller is statically reset. Other security mechanisms can also restrict these functions. If such mechanisms are present they are listed in the SAB address map section. 39.5.1.1 Notation Table 39-9 on page 1214 shows bit patterns to be shifted in a format like "peb01". Each character corresponds to one bit, and eight bits are grouped together for readability.
PAGE 1215
AT32UC3C Table 39-9. 39.5.2 39.5.2.1 Instruction Description (Continued) Instruction Description DR Size Shows the number of bits in the data register chain when this instruction is active. Example: 34 bits DR input value Shows which bit pattern to shift into the data register in the Shift-DR state when this instruction is active. Multiple such lines may exist, e.g., to distinguish between reads and writes.
PAGE 1216
AT32UC3C 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Capture-DR: The Data on the external pins are sampled into the boundary-scan chain. 7. In Shift-DR: The boundary-scan chain is shifted by the TCK input. 8. Return to Run-Test/Idle. Table 39-11. SAMPLE_PRELOAD Details 39.5.2.
PAGE 1217
AT32UC3C 39.5.2.4 INTEST This instruction selects the boundary-scan chain as Data Register for testing internal logic in the device. The logic inputs are determined by the boundary-scan chain, and the logic outputs are captured by the boundary-scan chain. The device output pins are driven from the boundary-scan chain. Starting in Run-Test/Idle, the INTEST instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3.
PAGE 1218
AT32UC3C 9. Return to Run-Test/Idle. Table 39-14. CLAMP Details 39.5.2.6 Instructions Details IR input value 00110 (0x06) IR output value p0001 DR Size 1 DR input value x DR output value x BYPASS This instruction selects the 1-bit Bypass Register as Data Register. Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3.
PAGE 1219
AT32UC3C Starting in Run-Test/Idle, OCD registers are accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the OCD register. 7. Go to Update-DR and re-enter Select-DR Scan. 8.
PAGE 1220
AT32UC3C 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a write operation, scan in the new contents of the register. 9. Return to Run-Test/Idle. For any operation, the full 7 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 39-17.
PAGE 1221
AT32UC3C The size field is encoded as i Table 39-18. Table 39-18.
PAGE 1222
AT32UC3C Table 39-19. MEMORY_SIZED_ACCESS Details (Continued) 39.5.3.4 Instructions Details DR output value (Address phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb DR output value (Data read phase) xxxxxeb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb MEMORY_WORD_ACCESS This instruction allows access to the entire Service Access Bus data area.
PAGE 1223
AT32UC3C Table 39-20. MEMORY_WORD_ACCESS Details (Continued) 39.5.3.5 Instructions Details DR output value (Address phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb DR output value (Data read phase) xeb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb MEMORY_BLOCK_ACCESS This instruction allows access to the entire SAB data area.
PAGE 1224
AT32UC3C Table 39-21. MEMORY_BLOCK_ACCESS Details (Continued) Instructions Details DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb The overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% transfer efficiency, or 2.1 MBytes per second with a 20 MHz TCK frequency. 39.5.3.
PAGE 1225
AT32UC3C 6. Scan in an 16-bit counter value. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: Scan out the busy bit, and until the busy bit clears goto 7. 9. Calculate an approximation to the internal clock speed using the elapsed time and the counter value. 10. Return to Run-Test/Idle. The full 16-bit counter value must be provided when starting the synch operation, or the result will be undefined.
PAGE 1226
AT32UC3C Table 39-24. AVR_RESET Details (Continued) 39.5.3.9 Instructions Details DR Size Device specific. DR input value Device specific. DR output value Device specific. CHIP_ERASE This instruction allows a programmer to completely erase all nonvolatile memories in a chip. This will also clear any security bits that are set, so the device can be accessed normally. In devices without non-volatile memories this instruction does nothing, and appears to complete immediately.
PAGE 1227
AT32UC3C 6. In Shift-DR: Scan in the value 1 to halt the CPU, 0 to start CPU execution. 7. Return to Run-Test/Idle. Table 39-26.
PAGE 1228
AT32UC3C 39.5.4 39.5.4.1 JTAG Data Registers The following device specific registers can be selected as JTAG scan chain depending on the instruction loaded in the JTAG Instruction Register. Additional registers exist, but are implicitly described in the functional description of the relevant instructions. Device Identification Register The Device Identification Register contains a unique identifier for each product.
PAGE 1229
AT32UC3C 39.5.4.2 Reset Register The reset register is selected by the AVR_RESET instruction and contains one bit for each reset domain in the device. Setting each bit to one will keep that domain reset until the bit is cleared. Bit Reset domain System 39.5.4.3 0 System Resets the whole chip, except the JTAG itself.
PAGE 1230
AT32UC3C 39.6 aWire Debug Interface (AW) Rev.: 2.3.0.1 39.6.1 Features • • • • • • • • 39.6.2 Single pin debug system. Half Duplex asynchronous communication (UART compatible). Full duplex mode for direct UART connection. Compatible with JTAG functionality, except boundary scan. Failsafe packet-oriented protocol. Read and write on-chip memory and program on-chip flash and fuses through SAB interface. On-Chip Debug access through SAB interface.
PAGE 1231
AT32UC3C 39.6.3 Block Diagram Figure 39-8. aWire Debug Interface Block Diagram PB aWire Debug Interface Flash Controller CHIP_ERASE command AW User Interface CPU HALT command RESET command Power Manager External reset AW_ENABLE AW CONTROL Reset filter RESET_N Baudrate Detector SAB interface UART RW SZ ADDR DATA CRC SAB 39.6.4 I/O Lines Description Table 39-28. I/O Lines Description Name Description Type DATA aWire data multiplexed with the RESET_N pin.
PAGE 1232
AT32UC3C 39.6.5.1 I/O Lines The pin used by AW is multiplexed with the RESET_N pin. The reset functionality is the default function of this pin. To enable the aWire functionality on the RESET_N pin the user must enable the AW either by sending the enable sequence over the RESET_N pin from an external aWire master or by enabling the aWire user interface. In 2-pin mode data is received on the RESET_N line, but transmitted on the DATAOUT line.
PAGE 1233
AT32UC3C The CRC is calculated from the command/response, length, and data fields. The polynomial used is the FCS16 (or CRC-16-CCIT) in reverse mode (0x8408) and the starting value is 0x0000. Example command Below is an example command from the master with additional data. Figure 39-9. Example Command baud_rate_clk data_pin field ... sync(0x55) command(0x81) length(MSB) length(lsb) data(MSB) data(LSB) CRC(MSB) CRC(lsb) ...
PAGE 1234
AT32UC3C 39.6.6.2 During the direction change there can be a period when the line is not driven. The internal pullup of the RESET_N pin keeps the signal stable when neither master or slave is actively driving the line. The RESET_N pin Normal reset functionality on the RESET_N pin is disabled when using aWire. However, the user can reset the system through the RESET aWire command.
PAGE 1235
AT32UC3C 39.6.6.7 Baud Rate Clock The communication speed is set by the master in the sync field of the command. The AW will use this to resynchronize its baud rate clock and reply on this frequency. The minimum frequency of the communication is 1 kHz. The maximum frequency depends on the internal clock source for the AW (RC120M).
PAGE 1236
AT32UC3C Two instructions exist to access the SAB: MEMORY_WRITE and MEMORY_READ. These two instructions write and read words, halfwords, and bytes from the SAB. Busy Reporting If the aWire master, during a MEMORY_WRITE or a MEMORY_READ command, transmit another byte when the aWire is still busy sending the previous byte to the SAB, the AW will respond with a MEMORY_READ_WRITE_STATUS error. See chapter Section 39.6.8.5 for more details.
PAGE 1237
AT32UC3C Table 39-30. aWire Command Summary COMMAND Instruction Description 0x07 DISABLE Disables the AW. 0x08 2_PIN_MODE Enables the DATAOUT pin and puts the aWire in 2-pin mode, where all responses are sent on the DATAOUT pin. 0x80 MEMORY_WRITE Writes words, halfwords, or bytes to the SAB. 0x81 MEMORY_READ Reads words, halfwords, or bytes from the SAB. 0x82 HALT Issues a halt command to the device. 0x83 RESET Issues a reset to the Reset Controller.
PAGE 1238
AT32UC3C 39.6.7.3 STATUS_REQUEST Asks the AW for a status message. Table 39-34. STATUS_REQUEST Details 39.6.7.4 Command Details Command value 0x03 Additional data N/A Possible responses 0xC4: STATUS_INFO (Section 39.6.8.7) 0x41: NACK (Section 39.6.8.2) TUNE Asks the AW for the current baud rate counter value. Table 39-35. TUNE Details 39.6.7.5 Command Details Command value 0x04 Additional data N/A Possible responses 0xC3: BAUD_RATE (Section 39.6.8.6) 0x41: NACK (Section 39.6.8.
PAGE 1239
AT32UC3C 39.6.7.7 DISABLE Disables the AW. The AW will respond with an ACK response and then disable itself. Table 39-38. DISABLE Details 39.6.7.8 Command Details Command value 0x07 Additional data N/A Possible responses 0x40: ACK (Section 39.6.8.1) 0x41: NACK (Section 39.6.8.2) 2_PIN_MODE Enables the DATAOUT pin as an output pin. All responses sent from the aWire slave will be sent on this pin, instead of the RESET_N pin, starting with the ACK for the 2_PIN_MODE command. Table 39-39.
PAGE 1240
AT32UC3C 4. 0x09 (length LSB) 5. 0x25 (size and address MSB, the two MSB of this byte are unused and set to zero) 6. 0x00 7. 0x00 8. 0x00 9. 0x04 (address LSB) 10. 0xCA 11. 0xFE 12. 0xBA 13. 0xBE 14. 0xXX (CRC MSB) 15. 0xXX (CRC LSB) The length field is set to 0x0009 because there are 9 bytes of additional data: 5 address and size bytes and 4 bytes of data. The address and size field indicates that words should be written to address 0x500000004. The data written to 0x500000004 is 0xCAFEBABE. Table 39-41.
PAGE 1241
AT32UC3C 1. 0x55 (sync) 2. 0x81 (command) 3. 0x00 (length MSB) 4. 0x07 (length LSB) 5. 0x25 (size and address MSB, the two MSB of this byte are unused and set to zero) 6. 0x00 7. 0x00 8. 0x00 9. 0x04 (address LSB) 10. 0x00 11. 0x04 12. 0xXX (CRC MSB) 13. 0xXX (CRC LSB) The length field is set to 0x0007 because there are 7 bytes of additional data: 5 bytes of address and size and 2 bytes with the number of bytes to read.
PAGE 1242
AT32UC3C and their destinations are identical to the resets described in the JTAG data registers chapter under reset register. Table 39-45. RESET Details 39.6.7.13 Command Details Command value 0x83 Additional data Reset value for each reset domain. The number of reset domains is part specific. Possible responses 0x40: ACK (Section 39.6.8.1) 0x41: NACK (Section 39.6.8.2) SET_GUARD_TIME Sets the guard time value in the AW, i.e.
PAGE 1243
AT32UC3C 39.6.8.1 ACK The AW has received the command successfully and performed the operation. Table 39-48. ACK Details 39.6.8.2 Response Details Response value 0x40 Additional data N/A NACK The AW has received the command, but got a CRC mismatch. Table 39-49. NACK Details 39.6.8.3 Response Details Response value 0x41 Additional data N/A IDCODE The JTAG idcode for this device. Table 39-50. IDCODE Details 39.6.8.
PAGE 1244
AT32UC3C 1. 0x55 (sync) 2. 0xC1 (command) 3. 0x00 (length MSB) 4. 0x07 (length LSB) 5. 0xCA (Data MSB) 6. 0xFE 7. 0xXX (An error has occurred. Data read is undefined. 5 bytes remaining of the Data field) 8. 0xXX (More undefined data) 9. 0x02 (Status byte) 10. 0x00 (Bytes remaining MSB) 11. 0x05 (Bytes remaining LSB) 12. 0xXX (CRC MSB) 13. 0xXX (CRC LSB) The error occurred after reading 2 bytes on the SAB. The rest of the bytes read are undefined.
PAGE 1245
AT32UC3C Table 39-54. MEMORY_READWRITE_STATUS Details 39.6.8.6 Response Details Response value 0xC2 Additional data Status byte and byte count (2 bytes) BAUD_RATE The current baud rate in the AW. See Section 39.6.6.7 for more details. Table 39-55. BAUD_RATE Details 39.6.8.7 Response Details Response value 0xC3 Additional data Baud rate STATUS_INFO A status message from AW. Table 39-56.
PAGE 1246
AT32UC3C Table 39-58. MEMORY_SPEED Details 39.6.9 Response Details Response value 0xC5 Additional data Clock cycle count (MS) Security Restrictions When the security fuse in the Flash is programmed, the following aWire commands are limited: • MEMORY_WRITE • MEMORY_READ Unlimited access to these instructions is restored when the security fuse is erased by the CHIP_ERASE aWire command.
PAGE 1247
AT32UC3C 39.7 Module Configuration The bit mapping of the Peripheral Debug Register (PDBG) is described in the following table. Please refer to the On-Chip Debug chapter in the AVR32UC Technical Reference Manual for details. Table 39-59.
PAGE 1248
AT32UC3C 40. Electrical Characteristics 40.1 Absolute Maximum Ratings* Operating temperature..................................... -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied.
PAGE 1249
AT32UC3C Table 40-2. Supply Rise Rates and Order Rise Rate Symbol Parameter Min Max VVDDIN_5 DC supply internal 3.3V regulator 0.01 V/ms 1.25 V/us VVDDIN_33 DC supply internal 1.8V regulator 0.01 V/ms 1.25 V/us VVDDIO1 VVDDIO2 VVDDIO3 DC supply peripheral I/O 0.01 V/ms 1.25 V/us Rise after or at the same time as VDDIN_5, VDDIN_33 VVDDANA DC supply peripheral I/O and analog part 0.01 V/ms 1.25 V/us Rise after or at the same time as VDDIN_5, VDDIN_33 40.
PAGE 1250
AT32UC3C – Internal 3.3V regulator is off • TA = 25°C • I/Os are configured as inputs, with internal pull-up enabled. • Oscillators – OSC0/1 (crystal oscillator) stopped – OSC32K (32KHz crystal oscillator) stopped – PLL0 running – PLL1 stopped • Clocks – External clock on XIN0 as main clock source (10MHz) – CPU, HSB, and PBB clocks undivided – PBA, PBC clock divided by 4 – All peripheral clocks running Table 40-4.
PAGE 1251
AT32UC3C Figure 40-1. Measurement Schematic VDDANA VDDIO Amp VDDIN_5 VDDIN_33 VDDCORE GNDCORE GNDPLL 40.4.1 Peripheral Power Consumption The values in Table 40-5 are measured values of power consumption under the following conditions. • Operating conditions core supply (Figure 40-1) – VVDDIN_5 = VDDIN_33 = 3.3V – VVDDCORE = 1.85V , supplied by the internal regulator – VVDDIO1 = VVDDIO2 = VVDDIO3 = 3.3V – VVDDANA = 3.3V – Internal 3.3V regulator is off.
PAGE 1252
AT32UC3C – PLL1 stopped • Clocks – External clock on XIN0 as main clock source. – CPU, HSB, and PB clocks undivided Consumption active is the added current consumption when the module clock is turned on and when the module is doing a typical set of operations. Table 40-5. Peripheral Typical Current Consumption by Peripheral(2) Typ Consumption Active (1) ACIFA (1) 3 ADCIFA 7 AST 3 CANIF 25 DACIFB(1) 3 EBI 23 EIC 0.5 FREQM 0.
PAGE 1253
AT32UC3C 40.5 I/O Pin Characteristics Normal I/O Pin Characteristics(1) Table 40-6. Symbol Parameter RPULLUP Pull-up resistance RPULLDOWN Pull-down resistance VIL Input low-level voltage VIH Input high-level voltage Condition Min VVDD = 3V VVDD = 5V Typ Max Units 5 26 kOhm 5 16 kOhm 2 16 kOhm VVDD = 3V 0.3*VVDDIO VVDD = 4.5V 0.3*VVDDIO VVDD = 3.6V 0.7*VVDDIO VVDD = 5.5V 0.7*VVDDIO V V IOL = -3.
PAGE 1254
AT32UC3C Normal I/O Pin Characteristics(1) Table 40-6. Symbol Parameter Condition VVDD = 3.0V tRISE Rise time(3) VVDD = 4.5V VVDD = 3.0V tFALL Fall time(3) VVDD = 4.5V ILEAK CIN Min Max load = 10pF, pin drive x1 7.7 load = 10pF, pin drive x2 (2) 3.4 load = 10pF, pin drive x4 (2) 1.9 load = 30pF, pin drive x1(2) 16 load = 30pF, pin drive x2(2) 7.5 load = 30pF, pin drive x4 (2) 3.8 load = 10pF, pin drive x1 (2) 5.3 load = 10pF, pin drive x2(2) 2.
PAGE 1255
AT32UC3C 40.6 Oscillator Characteristics 40.6.1 Oscillator (OSC0 and OSC1) Characteristics 40.6.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN0 or XIN1. Table 40-7. Digital Clock Characteristics Symbol Parameter fCPXIN XIN clock frequency tCPXIN XIN clock period tCHXIN XIN clock high half-priod 0.4 x tCPXIN 0.6 x tCPXIN ns tCLXIN XIN clock low half-priod 0.4 x tCPXIN 0.
PAGE 1256
AT32UC3C Table 40-8. Crystal Oscillator Characteristics Symbol Parameter fOUT Crystal oscillator frequency Ci Internal equivalent load capacitance tSTARTUP Notes: Conditions Min Typ 0.4 Max Unit 20 MHz 1.7 pF fOUT = 8MHz SCIF.OSCCTRL.GAIN = 1(1) 975 us fOUT = 16MHz SCIF.OSCCTRL.GAIN = 2(1) 1100 us Startup time 1. Please refer to the SCIF chapter for details. 40.6.2 32KHz Crystal Oscillator (OSC32K) Characteristics 40.6.2.
PAGE 1257
AT32UC3C 40.6.3 Phase Lock Loop (PLL0 and PLL1) Characteristics Table 40-11. PLL Characteristics Symbol Parameter fVCO Output frequency fIN Input frequency IPLL Current consumption tSTARTUP Startup time, from enabling the PLL until the PLL is locked 40.6.
PAGE 1258
AT32UC3C 40.7 Flash Characteristics Table 40-15 gives the device maximum operating frequency depending on the number of flash wait states. The FSW bit in the FLASHC FSR register controls the number of wait states used when accessing the flash memory. Table 40-15. Maximum Operating Frequency Flash Wait States Read Mode Maximum Operating Frequency 0 1 cycle 33MHz 1 2 cycles 66MHz Table 40-16.
PAGE 1259
AT32UC3C 40.8 Analog Characteristics 40.8.1 1.8V Voltage Regulator Characteristics Table 40-18. 1.8V Voltage Regulator Electrical Characteristics Symbol Parameter VVDDIN_5 Input voltage range VVDDCORE Output voltage, calibrated value IOUT DC output current Condition Min Typ Max 5V range 4.5 5.5 3V range 3.0 3.6 Units V 1.85 V 80 mA Table 40-19. Decoupling Requirements Symbol Parameter CIN1 Typ Techno.
PAGE 1260
AT32UC3C 40.8.4 3.3V Brown Out Detector (BOD33) Characteristics The values in Table 40-23 describe the values of the BOD33.LEVEL field in the SCIF module. Table 40-23. BOD33.LEVEL Values BOD33.LEVEL Value Parameter Min Max 17 2.21 2.55 22 2.30 2.64 27 2.39 2.74 2.46 2.82 33 2.50 2.86 39 2.60 2.98 44 2.69 3.08 49 2.78 3.18 53 2.85 3.27 60 2.98 3.41 31 threshold at power-up sequence Units V 40.8.
PAGE 1261
AT32UC3C 40.8.6 Analog to Digital Converter (ADC) and sample and hold (S/H) Characteristics Table 40-27. ADC and S/H characteristics Symbol fADC Parameter ADC clock frequency Conditions Min Typ 12-bit resolution mode, VVDDANA = 3V 1.2 10-bit resolution mode, VVDDANA = 3V 1.6 8-bit resolution mode, VVDDANA = 3V 2.2 12-bit resolution mode, VVDDANA = 4.5V 1.5 10-bit resolution mode, VVDDANA = 4.5V 2 8-bit resolution mode, VVDDANA = 4.5V 2.
PAGE 1262
AT32UC3C Table 40-29. ADC Decoupling requirements Symbol Parameter Conditions Min CADCREFPN ADCREFP/ADCREFN capacitance No voltage reference appplied on ADCREFP/ADCREFN Typ Max 100 Units nF Table 40-30. ADC Inputs Symbol Parameter VADCINn ADC input voltage range Conditions CONCHIP Internal Capacitance RONCHIP Switch resistance Min Typ 0 Max Units VVDDANA V ADC used without S/H 5 ADC used with S/H 4 ADC used without S/H 5.1 ADC used with S/H 4.6 pF kΩ Figure 40-3.
PAGE 1263
AT32UC3C Table 40-31. ADC Transfer Characteristics (Continued)12-bit Resolution Mode(1) Symbol Parameter Conditions Differential mode, VVDDANA = 5V, VADCREF0 = 3V, ADCFIA.SEQCFGn.SRES = 0 (Fadc = 1.5MHz) RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Offset error Gain error Note: Min Typ Max Units 12 Bit 4 LSB 3 LSB -15 15 mV -25 25 mV Max Units 10 Bit 1.25 LSB 1. The measures are done without any I/O activity on VDDANA/GNDANA power domain.
PAGE 1264
AT32UC3C Table 40-34. ADC and S/H Transfer Characteristics 12-bit Resolution Mode and S/H gain = 1(1) Symbol Parameter Conditions RES Resolution INL Integral Non-Linearity Differential mode, VVDDANA = 3V, VADCREF0 = 1V, ADCFIA.SEQCFGn.SRES = 0, S/H gain = 1 (Fadc = 1.2MHz) DNL Differential Non-Linearity Offset error Gain error RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Offset error Gain error Note: Differential mode, VVDDANA = 5V, VADCREF0 = 3V, ADCFIA.
PAGE 1265
AT32UC3C Table 40-36. ADC and S/H Transfer Characteristics (Continued)10-bit Resolution Mode and S/H gain from 1 to 16(1) Symbol Parameter Conditions Differential mode, VVDDANA = 5V, VADCREF0 = 3V, ADCFIA.SEQCFGn.SRES = 1, S/H gain from 1 to 16 (Fadc = 1.5MHz) RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Offset error Gain error Note: Min Typ Max Units 10 Bit 1.5 LSB 1.5 LSB -25 25 mV -15 15 mV Max Units 1.
PAGE 1266
AT32UC3C Figure 40-4. DAC output UC3C DAC0A S/H CLOAD DAC RLOAD Table 40-40.
PAGE 1267
AT32UC3C 40.8.8 Analog Comparator Characteristics Table 40-41.
PAGE 1268
AT32UC3C 40.9 Timing Characteristics 40.9.1 Startup, Reset, and Wake-up Timing The startup, reset, and wake-up timings are calculated using the following formula: t = t CONST + N CPU × t CPU Where t CONST and N CPU are found in Table 40-44. t CONST is the delay relative to RCSYS, t CPU is the period of the CPU clock. If another clock source than RCSYS is selected as CPU clock the startup time of the oscillator, t OSCSTART , must be added to the wake-up time in the stop, deepstop, and static sleep modes.
PAGE 1269
AT32UC3C Figure 40-5. Startup and Reset Time Voltage VDDIN_5, VDDIN_33 BOD33 threshold at power-up VDDCORE BOD18 threshold at power-up Time Internal Reset 40.9.2 Reset Time Startup Time from reset Release Decoding Stage RESET_N characteristics Table 40-45. RESET_N Clock Waveform Parameters Symbol Parameter tRESET RESET_N minimum pulse length Condition Min. 2 * TRCSYS Typ. Max.
PAGE 1270
AT32UC3C 40.9.3 USART in SPI Mode Timing 40.9.3.1 Master mode Figure 40-6. USART in SPI Master Mode With (CPOL= CPHA= 0) or (CPOL= CPHA= 1) SPCK MISO USPI0 USPI1 MOSI USPI2 Figure 40-7. USART in SPI Master Mode With (CPOL= 0 and CPHA= 1) or (CPOL= 1 and CPHA= 0) SPCK MISO USPI3 USPI4 MOSI USPI5 Table 40-46.
PAGE 1271
AT32UC3C Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: 1 f CLKSPI × 2 f SPCKMAX = MIN (f PINMAX,------------, -----------------------------) SPIn 9 Where SPIn is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA. f PINMAX is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. f CLKSPI is the maximum frequency of the CLK_SPI.
PAGE 1272
AT32UC3C Figure 40-9. USART in SPI Slave Mode With (CPOL= CPHA= 0) or (CPOL= CPHA= 1) SPCK MISO USPI9 MOSI USPI10 USPI11 Figure 40-10. USART in SPI Slave Mode NPCS Timing USPI12 USPI13 USPI14 USPI15 SPCK, CPOL=0 SPCK, CPOL=1 NSS Table 40-47.
PAGE 1273
AT32UC3C Maximum SPI Frequency, Slave Input Mode The maximum SPI slave input frequency is given by the following formula: f CLKSPI × 2 1 f SPCKMAX = MIN (----------------------------,------------) 9 SPIn Where SPIn is the MOSI setup and hold time, USPI7 + USPI8 or USPI10 + USPI11 depending on CPOL and NCPHA. f CLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock.
PAGE 1274
AT32UC3C Figure 40-12. SPI Master Mode With (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK MISO SPI3 SPI4 MOSI SPI5 Table 40-48. SPI Timing, Master Mode(1) Symbol Parameter SPI0 MISO setup time before SPCK rises SPI1 MISO hold time after SPCK rises SPI2 SPCK rising to MOSI delay SPI3 MISO setup time before SPCK falls SPI4 MISO hold time after SPCK falls SPI5 SPCK falling to MOSI delay Note: Conditions external capacitor = 40pF Min Max Units 28.5+ (tCLK_SPI)/2 ns 0 ns 10.
PAGE 1275
AT32UC3C 40.9.4.2 Slave mode Figure 40-13. SPI Slave Mode With (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK MISO SPI6 MOSI SPI7 SPI8 Figure 40-14. SPI Slave Mode With (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1) SPCK MISO SPI9 MOSI SPI10 SPI11 Figure 40-15.
PAGE 1276
AT32UC3C Table 40-49.
PAGE 1277
AT32UC3C TWIM and TWIS user interface registers. Please refer to the TWIM and TWIS sections for more information. Table 40-50. TWI-Bus Timing Requirements Minimum Symbol Parameter Mode Requirement Standard(1) tr TWCK and TWD rise time tf TWCK and TWD fall time tHD-STA (Repeated) START hold time tSU-STA (Repeated) START set-up time tSU-STO STOP set-up time tHD-DAT Data hold time tLOW-I2C Standard(1) 4.0 Fast(1) 0.6 Standard(1) 4.7 Fast(1) 0.6 Standard(1) 4.0 Fast(1) 0.
PAGE 1278
AT32UC3C 40.9.6 JTAG Timing Figure 40-16. JTAG Interface Signals JTAG2 TCK JTAG0 JTAG1 TMS/TDI JTAG3 JTAG4 JTAG7 JTAG8 TDO JTAG5 JTAG6 Boundary Scan Inputs Boundary Scan Outputs JTAG9 JTAG10 Table 40-51. JTAG Timings(1) Symbol Parameter JTAG0 TCK Low Half-period 21.5 ns JTAG1 TCK High Half-period 8.5 ns JTAG2 TCK Period 29 ns JTAG3 TDI, TMS Setup before TCK High 6.5 ns JTAG4 TDI, TMS Hold after TCK High 0 ns JTAG5 TDO Hold Time 12.
PAGE 1279
AT32UC3C 40.9.7 EBI Timings See EBI I/O lines description for more details. Table 40-52. SMC Clock Signal. Symbol Parameter 1/(tCPSMC) SMC Controller clock frequency Note: Max(1) Units fcpu MHz 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB. Table 40-53.
PAGE 1280
AT32UC3C Table 40-54. SMC Read Signals with no Hold Settings(1) Symbol Parameter Conditions Min Units NRD Controlled (READ_MODE = 1) SMC19 Data setup before NRD high SMC20 Data hold after NRD high VVDD = 3.0V, drive strength of the pads set to the lowest, external capacitor = 40pF 32.5 ns 0 NRD Controlled (READ_MODE = 0) SMC21 Data setup before NCS high SMC22 Data hold after NCS high Note: VVDD = 3.0V, drive strength of the pads set to the lowest, external capacitor = 40pF 28.5 ns 0 1.
PAGE 1281
AT32UC3C Table 40-56. SMC Write Signals with No Hold Settings (NWE Controlled only)(1) Symbol Parameter SMC37 NWE rising to A2-A25 valid 8.7 SMC38 NWE rising to NBS0/A0 valid 7.6 SMC40 NWE rising to A1/NBS2 change SMC42 NWE rising to NCS rising SMC43 Data Out valid before NWE rising SMC44 Data Out valid after NWE rising SMC45 NWE pulse width Note: Conditions Min VVDD = 3.0V, drive strength of the pads set to the lowest, external capacitor = 40pF Units 8.7 8.
PAGE 1282
AT32UC3C Figure 40-18. SMC Signals for NRD and NRW Controlled Accesses(1) SMC37 SMC7 SMC7 SMC31 A2-A25 SMC25 SMC26 SMC29 SMC30 SMC3 SMC4 SMC5 SMC6 SMC38 SMC39 SMC40 SMC41 SMC3 SMC4 SMC5 SMC6 A0/A1/NBS[3:0] SMC42 SMC32 SMC8 NCS SMC8 SMC9 SMC9 NRD SMC19 SMC20 SMC43 SMC44 SMC1 SMC23 SMC2 SMC24 D0 - D15 SMC45 SMC33 NWE Note: 40.9.8 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology.
PAGE 1283
AT32UC3C Table 40-58. SDRAM Signal(1) Symbol Parameter Conditions Min SDRAMC1 SDCKE high before SDCK rising edge 5.6 SDRAMC2 SDCKE low after SDCK rising edge 7.3 SDRAMC3 SDCKE low before SDCK rising edge 6.8 SDRAMC4 SDCKE high after SDCK rising edge 8.3 SDRAMC5 SDCS low before SDCK rising edge 6.1 SDRAMC6 SDCS high after SDCK rising edge 8.4 SDRAMC7 RAS low before SDCK rising edge 7 SDRAMC8 RAS high after SDCK rising edge 7.7 SDRAMC9 SDA10 change before SDCK rising edge 6.
PAGE 1284
AT32UC3C Figure 40-19. SDRAMC Signals relative to SDCK.
PAGE 1285
AT32UC3C 40.9.9 MACB Characteristics Table 40-59. Ethernet MAC Signals(1) Symbol Parameter MAC1 Setup for MDIO from MDC rising MAC2 Hold for MDIO from MDC rising MAC3 MDIO toggling from MDC falling Note: Conditions Min. Max. Unit VVDD = 3.0V, drive strength of the pads set to the highest, external capacitor = 10pF on MACB pins 0 2.5 ns 0 0.7 ns 0 1.1 ns 1.
PAGE 1286
AT32UC3C Figure 40-20.
PAGE 1287
AT32UC3C Table 40-61. Ethernet MAC RMII Specific Signals(1) Symbol Parameter Conditions Min. Max. Unit MAC21 TX_EN toggling from TX_CLK rising 11.7 12.5 ns MAC22 TXD toggling from TX_CLK rising 11.7 12.5 ns MAC23 Setup for RXD from TX_CLK MAC24 Hold for RXD from TX_CLK MAC25 Setup for RX_ER from TX_CLK MAC26 Hold for RX_ER from TX_CLK MAC27 MAC28 Note: 4.5 ns 0 ns 3.4 ns 0 ns Setup for RX_DV from TX_CLK 4.4 ns Hold for RX_DV from TX_CLK 0 ns VVDD = 3.
PAGE 1288
AT32UC3C 41. Mechanical Characteristics 41.1 41.1.1 Thermal Considerations Thermal Data Table 41-1 summarizes the thermal resistance data depending on the package. Table 41-1. 41.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ θJA Junction-to-ambient thermal resistance No air flow QFN64 20.0 θJC Junction-to-case thermal resistance QFN64 0.8 θJA Junction-to-ambient thermal resistance TQFP64 40.5 θJC Junction-to-case thermal resistance TQFP64 8.
PAGE 1289
AT32UC3C 41.2 Package Drawings Figure 41-1. QFN-64 package drawing Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 41-2. Device and Package Maximum Weight 200 Table 41-3. mg Package Characteristics Moisture Sensitivity Level Table 41-4.
PAGE 1290
AT32UC3C Figure 41-2. TQFP-64 package drawing Table 41-5. Device and Package Maximum Weight 300 Table 41-6. mg Package Characteristics Moisture Sensitivity Level Table 41-7.
PAGE 1291
AT32UC3C Figure 41-3. TQFP-100 package drawing Table 41-8. Device and Package Maximum Weight 500 Table 41-9. mg Package Characteristics Moisture Sensitivity Level Jdec J-STD0-20D - MSL 3 Table 41-10.
PAGE 1292
AT32UC3C Figure 41-4. LQFP-144 package drawing Table 41-11. Device and Package Maximum Weight 1300 mg Table 41-12. Package Characteristics Moisture Sensitivity Level Jdec J-STD0-20D - MSL 3 Table 41-13.
PAGE 1293
AT32UC3C 41.3 Soldering Profile Table 41-14 gives the recommended soldering profile from J-STD-20. Table 41-14. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec Preheat Temperature 175°C ±25°C Min. 150 °C, Max. 200 °C Temperature Maintained Above 217°C 60-150 sec Time within 5⋅C of Actual Peak Temperature 30 sec Peak Temperature Range 260 °C Ramp-down Rate 6 °C/sec Time 25⋅C to Peak Temperature Max.
PAGE 1294
AT32UC3C 42. Ordering Information Table 42-1.
PAGE 1295
AT32UC3C 43. Errata 43.1 43.1.1 43.1.2 43.1.3 rev E ADCIFA 1 ADCREFP/ADCREFN can not be selected as an external ADC reference by setting the ADCIFA.CFG.EXREF bit to one Fix/Workaround A voltage reference can be applied on ADCREFP/ADCREFN pins if the ADCIFA.CFG.EXREF bit is set to zero, the ADCIFA.CFG.RS bit is set to zero and the voltage reference applied on ADCREFP/ADCREFN pins is higher than the internal 1V reference.
PAGE 1296
AT32UC3C 43.1.5 43.1.6 SCIF 1 PLLCOUNT value larger than zero can cause PLLEN glitch Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN signal during asynchronous wake up. Fix/Workaround The lock-masking mechanism for the PLL should not be used. The PLLCOUNT field of the PLL Control Register should always be written to zero.
PAGE 1297
AT32UC3C 43.1.7 43.1.8 4 SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0.
PAGE 1298
AT32UC3C Fix/Workaround None. 43.1.11 3 In host mode, the disconnection during OUT transition is not supported In USB host mode, a pipe can not work if the previous USB device disconnection has occurred during a USB transfer. Fix/Workaround Reset the USBC (USBCON.USB=0 and =1) after a device disconnection (UHINT.DDISCI). 4 In USB host mode, entering suspend mode can fail In USB host mode, entering suspend mode can fail when UHCON.SOFE=0 is done just after a SOF reception (UHINT.HSOFI).
PAGE 1299
AT32UC3C 43.2 43.2.1 43.2.2 43.2.3 rev D ADCIFA 1 ADCREFP/ADCREFN can not be selected as an external ADC reference by setting the ADCIFA.CFG.EXREF bit to one Fix/Workaround A voltage reference can be applied on ADCREFP/ADCREFN pins if the ADCIFA.CFG.EXREF bit is set to zero, the ADCIFA.CFG.RS bit is set to zero and the voltage reference applied on ADCREFP/ADCREFN pins is higher than the internal 1V reference.
PAGE 1300
AT32UC3C 43.2.6 43.2.7 2 Requesting clocks in idle sleep modes will mask all other PB clocks than the requested In idle or frozen sleep mode, all the PB clocks will be frozen if the TWIS or the AST need to wake the cpu up. Fix/Workaround Disable the TWIS or the AST before entering idle or frozen sleep mode. 3 TWIS may not wake the device from sleep mode If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condition, the CPU may not wake upon a TWIS address match.
PAGE 1301
AT32UC3C 43.2.8 43.2.9 2 Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA.
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AT32UC3C 43.2.10 43.2.11 TWIS 1 Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set.
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AT32UC3C 43.2.12 WDT 1 Clearing the Watchdog Timer (WDT) counter in second half of timeout period will issue a Watchdog reset If the WDT counter is cleared in the second half of the timeout period, the WDT will immediately issue a Watchdog reset. Fix/Workaround Use twice as long timeout period as needed and clear the WDT counter within the first half of the timeout period. If the WDT counter is cleared after the first half of the timeout period, you will get a Watchdog reset immediately.
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AT32UC3C 44. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 44.1 44.2 44.3 Rev. D – 01/12 1 Errata: Updated 2 PM: Clock Mask Table Updated 3 Fixed PLLOPT field description in SCIF chapter 4 MDMA: Swapped bit descriptions for IER and IDR 5 MACB: USRIO register description and bit descriptions for IMR/IDR/IER Updated 6 USBC: UPCON.
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AT32UC3C 44.4 5 AST: Updated digital tuner formula 6 SDRAMC: cleaned-up SDCS/NCS names. Added VERSION register 7 SAU: Updated SR.IDLE 8 USART: Updated 9 CANIF: Updated address map figure 10 USBC: Updated 11 DACIFB: Updated 12 Programming and Debugging: Added JTAG Data Registers section 13 Electrical Characteristics: Updated 14 Ordering Information: Updated 15 Errata: Updated 1 Initial revision Rev.
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AT32UC3C Table of Content 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 4 5 6 7 2.1 Block diagram ....................................................................................................5 2.2 Configuration Summary .....................................................................................
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AT32UC3C 8 9 System Control Interface (SCIF) ........................................................... 82 8.1 Features ..........................................................................................................82 8.2 Description .......................................................................................................82 8.3 I/O Lines Description .......................................................................................82 8.4 Product Dependencies ..........
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AT32UC3C 12.3 Block Diagram ...............................................................................................188 12.4 I/O Lines Description .....................................................................................189 12.5 Product Dependencies ..................................................................................189 12.6 Functional Description ...................................................................................189 12.7 User Interface .............
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AT32UC3C 15.12 Module Configuration ....................................................................................285 16 HSB Bus Matrix (HMATRIXB) .............................................................. 286 16.1 Features ........................................................................................................286 16.2 Overview ........................................................................................................286 16.3 Product Dependencies ...............
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AT32UC3C 20.1 Features ........................................................................................................375 20.2 Overview ........................................................................................................375 20.3 Block Diagram ...............................................................................................376 20.4 Product Dependencies ..................................................................................376 20.
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AT32UC3C 24.1 Features ........................................................................................................488 24.2 Overview ........................................................................................................488 24.3 Block Diagram ...............................................................................................489 24.4 Product Dependencies ..................................................................................489 24.
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AT32UC3C 27.7 Product Dependencies ..................................................................................700 27.8 Functional Description ...................................................................................702 27.9 User Interface ................................................................................................714 27.10 Module Configuration ....................................................................................
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AT32UC3C 31.1 Features ........................................................................................................829 31.2 Overview ........................................................................................................829 31.3 Block Diagram ...............................................................................................830 31.4 I/O Lines Description .....................................................................................830 31.
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AT32UC3C 35 Analog Comparator Interface (ACIFA) ............................................. 1074 35.1 Features ......................................................................................................1074 35.2 Overview ......................................................................................................1074 35.3 Block Diagram .............................................................................................1075 35.4 I/O Lines Description ....................
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AT32UC3C 38.8 Module Configuration ..................................................................................1193 39 Programming and Debugging .......................................................... 1194 39.1 Overview ......................................................................................................1194 39.2 Service Access Bus .....................................................................................1194 39.3 On-Chip Debug ....................................
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Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg.