Datasheet

735
AT32UC3A
35.3 Block diagram
Figure 35-1. On-Chip Debug block diagram
35.4 Functional description
35.4.1 JTAG-based debug features
A debugger can control all OCD features by writing OCD registers over the JTAG interface.
Many of these do not depend on output on the AUX port, allowing a JTAG-based debugger to be
used.
A JTAG-based debugger should connect to the device through a standard 10-pin IDC connector
as described in the AVR32UC Technical Reference Manual.
On-Chip Debug
JTAG
Debug PC
Debug
Instruction
CPU
Breakpoints
Program
Trace
Data Trace
Ownership
Trace
WatchpointsTransmit Queue
AUX
JTAG
Internal
SRAM
S
e
r
v
ic
e
A
c
c
e
s
s
B
u
s
Memory
Service
Unit
HSB Bus Matrix
Memories and
peripherals
32058K
AVR32-01/12