Datasheet

699
AT32UC3A
33. Analog-to-Digital Converter (ADC)
Rev: 1.0.0.3
33.1 Features
• Integrated Multiplexer Offering Up to Eight Independent Analog Inputs
• Individual Enable and Disable of Each Channel
• Hardware or Software Trigger
– External Trigger Pin
–Timer Counter Outputs (Corresponding TIOA Trigger)
• PDC Support
• Possibility of ADC Timings Configuration
• Sleep Mode and Conversion Sequencer
– Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all Enabled
Channels
33.2 Overview
The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Con-
verter (ADC). It also integrates an ADC_NB_CHANNELS-to-1 analog multiplexer, making
possible the analog-to-digital conversions of ADC_NB_CHANNELS analog lines. The conver-
sions extend from 0V to ADVREF.
The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a
common register for all channels, as well as in a channel-dedicated register. Software trigger,
external trigger on rising edge of the TRIGGER pin or internal triggers from Timer Counter out-
put(s) are configurable.
The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC
channel. These features reduce both power consumption and processor intervention.
Finally, the user can configure ADC timings, such as Startup Time and Sample & Hold Time.
32058K
AVR32-01/12