Datasheet
691
AT32UC3A
32.7.8 PWM Interrupt Mask Register
Register Name: IMR
Access Type: Read-only
• CHIDx: Channel ID.
0 = Interrupt for PWM channel x is disabled.
1 = Interrupt for PWM channel x is enabled.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– CHID6 CHID5 CHID4 CHID3 CHID2 CHID1 CHID0
32058K
AVR32-01/12