Datasheet
624
AT32UC3A
30.8.3.16 USB Pipe X Control Register (UPCONX)
Offset: 0x05C0 + X . 0x04
Register Name: UPCONX, X in [0..6]
Access Type: Read-Only
Reset Value: 0x00000000
• RXINE: Received IN Data Interrupt Enable
Set by software (by setting the RXINES bit) to enable the Received IN Data interrupt (RXINE).
Clear by software (by setting the RXINEC bit) to disable the Received IN Data interrupt (RXINE).
• TXOUTE: Transmitted OUT Data Interrupt Enable
Set by software (by setting the TXOUTES bit) to enable the Transmitted OUT Data interrupt (TXOUTE).
Clear by software (by setting the TXOUTECbit) to disable the Transmitted OUT Data interrupt (TXOUTE).
• TXSTPE: Transmitted SETUP Interrupt Enable
Set by software (by setting the TXSTPES bit) to enable the Transmitted SETUP interrupt (TXSTPE).
Clear by software (by setting the TXSTPEC bit) to disable the Transmitted SETUP interrupt (TXSTPE).
• UNDERFIE: Underflow Interrupt Enable
Set by software (by setting the UNDERFIES bit) to enable the Underflow interrupt (UNDERFIE).
Clear by software (by setting the UNDERFIEC bit) to disable the Underflow interrupt (UNDERFIE).
• PERRE: Pipe Error Interrupt Enable
Set by software (by setting the PERRES bit) to enable the Pipe Error interrupt (PERRE).
Clear by software (by setting the PERREC bit) to disable the Pipe Error interrupt (PERRE).
• NAKEDE: NAKed Interrupt Enable
Set by software (by setting the NAKEDES bit) to enable the NAKed interrupt (NAKEDE).
Clear by software (by setting the NAKEDEC bit) to disable the NAKed interrupt (NAKEDE).
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – RSTDT PFREEZE PDISHDMA
ru ru ru
0 0 0
15 14 13 12 11 10 9 8
– FIFOCON – NBUSYBKE – – – –
ru ru
0 0
7 6 5 4 3 2 1 0
SHORT
PACKETIE
RXSTALLDE/
CRCERRE
OVERFIE NAKEDE PERRE
TXSTPE/
UNDERFIE
TXOUTE RXINE
ru ru ru ru ru ru ru ru
0 0 0 0 0 0 0 0
32058K
AVR32-01/12