Datasheet

AT32UC3A

30.8.2.9 USB Endpoint Enable/Reset Register (UERST)

Offset: 0x001C

Access Type: Read/Write

Reset Value: 0x00000000

• EPENX, X in [0..6]: Endpoint X Enable

Set to enable the endpoint X.

Clear to disable the endpoint X, what forces the endpoint X state to inactive (no answer to USB requests) and resets the

endpoint X registers (UECFGX, UESTAX, UECONX) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR,

EPTYPE).

• EPRSTX, X in [0..6]: Endpoint X Reset

Set by software to reset the endpoint X FIFO prior to any other operation, upon hardware reset or when a USB bus reset

has been received. This resets the endpoint X registers (UECFGX, UESTAX, UECONX) but not the endpoint configuration

(ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).

All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence

field (DTSEQ) which can be cleared by setting the RSTDT bit (by setting the RSTDTS bit).

The endpoint configuration remains active and the endpoint is still enabled.

Then, clear by software to complete the reset operation and to start using the FIFO.

Cleared by hardware upon receiving a USB reset.

31 30 29 28 27 26 25 24

– – – – – – – –

23 22 21 20 19 18 17 16

– EPRST6 EPRST5 EPRST4 EPRST3 EPRST2 EPRST1 EPRST0

rwu rwu rwu rwu rwu rwu rwu

0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

– – – – – – – –

7 6 5 4 3 2 1 0

– EPEN6 EPEN5 EPEN4 EPEN3 EPEN2 EPEN1 EPEN0

rw rw rw rw rw rw rw

0 0 0 0 0 0 0

32058K

AVR32-01/12