Datasheet

57
AT32UC3A
divide the output of the PLL by two and bring the clock in range of the max frequency of the
CPU.
When the PLL is switched on, or when changing the clock source or multiplication factor for the
PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital
logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from
receiving a too high frequency and thus become unstable.
Figure 13-3. PLL with control logic and filters
13.5.4.1 Enabling the PLL
PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1
as clock source. The PLLMUL and PLLDIV bitfields must be written with the multiplication and
division factors, respectively, creating the voltage controlled ocillator frequency f
VCO
and the PLL
frequency f
PLL
:
f
VCO
= (PLLMUL+1)/(PLLDIV) • f
OSC
if PLLDIV > 0.
f
VCO
= 2*(PLLMUL+1) • f
OSC
if PLLDIV = 0.
If PLLOPT[1] field is set to 0:
f
PLL
= f
VCO.
If PLLOPT[1] field is set to 1:
f
PLL
= f
VCO
/ 2
.
The PLLn:PLLOPT field should be set to proper values according to the PLL operating fre-
quency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2.
The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be gen-
erated on a 0 to 1 transition of these bits.
Phase
Detector
Output
Divider
0
1
Osc0
clock
Osc1
clock
PLLOSC
PLLOPT
PLLMU L
Lock bit
Mask
PLL clock
In p u t
D ivider
PLLDIV
1/2
PLLOPT[1]
0
1
VC O
f
vco
f
PLL
Lock
Detector
32058K
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