Datasheet

515
AT32UC3A
•the Received OUT Data interrupt (RXOUTI) which is raised when a new OUT packet is
received and which shall be cleared by firmware to acknowledge the packet and to free the
bank;
•the Transmitted IN Data interrupt (TXINI) which is raised when the current bank is ready to
accept a new IN packet and which shall be cleared by firmware to send the packet.
30.7.2.11.2 Control Write
Figure 30-15 shows a control write transaction. During the status stage, the controller will not
necessarily send a NAK on the first IN token:
•if the firmware knows the exact number of descriptor bytes that must be read, it can then
anticipate the status stage and send a zero-length packet after the next IN token;
•or it can read the bytes and wait for the NAKed IN interrupt (NAKINI) which tells that all the
bytes have been sent by the host and that the transaction is now in the status stage.
Figure 30-15. Control Write
30.7.2.11.3 Control Read
Figure 30-16 shows a control read transaction. The USB controller has to manage the simulta-
neous write requests from the CPU and the USB host.
Figure 30-16. Control Read
A NAK handshake is always generated on the first status stage command.
When the controller detects the status stage, all the data written by the CPU is lost and clearing
TXINI has no effect.
The firmware checks if the transmission or the reception is complete.
SETUP
RXSTPI
RXOUTI
TXINI
USB Bus
HW SW
OUT
HW SW
OUT
HW SW
IN IN
NAK
SW
DATASETUP STATUS
SETUP
RXSTPI
RXOUTI
TXINI
USB Bus
HW SW
IN
HW SW
IN OUT OUT
NAK
SW
SW
HW
Wr Enable
HOST
Wr Enable
CPU
DATASETUP STATUS
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AVR32-01/12