Datasheet

422
AT32UC3A
Figure 28-10. Low-power Mode Behavior
28.7.5.3 Deep Power-down Mode
This mode is selected by programming the LPCB field to 3 in the SDRAMC Low Power Register.
When this mode is activated, all internal voltage generators inside the SDRAM are stopped and
all data is lost.
When this mode is enabled, the application must not access to the SDRAM until a new initializa-
tion sequence is done (See ”SDRAM Device Initialization” on page 415).
This is described in Figure 28-11.
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
D[31:0]
(input)
T
RCD
= 3
Dna Dnb Dnc Dnd
Dne Dnf
Row n col a col b col c col d col e col f
CAS = 2
SDCKE
Low Power Mode
32058K
AVR32-01/12