Datasheet

419
AT32UC3A
Figure 28-7. Read Burst with Boundary Row Access
28.7.4 SDRAM Controller Refresh Cycles
An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated internally by the SDRAM device and incremented after each auto-refresh automatically.
The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is
loaded with the value in the register TR that indicates the number of clock cycles between
refresh cycles.
A refresh error interrupt is generated when the previous auto-refresh command did not perform.
It is acknowledged by reading the Interrupt Status Register (ISR).
When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses
are not delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the
device is busy and the master is held by a wait signal. See Figure 28-8.
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
D[31:0]
T
RP
= 3
SDWE
Row m
col a
col a col b col c col d col e
Dna Dnb
Dnc Dnd
T
RCD
= 3 CAS = 2
col b
col c
col d
Dma Dmb
Dmc
Dmd
Row n
Dme
32058K
AVR32-01/12