Datasheet

414
AT32UC3A
28.5.2.2 16-bit Memory Data Bus Width
Notes: 1. M0 is the byte address inside a 16-bit half-word.
2. Bk[1] = BA1, Bk[0] = BA0.
Table 28-5. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[10:0] Column[7:0]
M
0
Bk[1:0] Row[10:0] Column[8:0]
M
0
Bk[1:0] Row[10:0] Column[9:0]
M
0
Bk[1:0] Row[10:0] Column[10:0]
M
0
Table 28-6. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[11:0] Column[7:0]
M
0
Bk[1:0] Row[11:0] Column[8:0]
M
0
Bk[1:0] Row[11:0] Column[9:0]
M
0
Bk[1:0] Row[11:0] Column[10:0]
M
0
Table 28-7. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[12:0] Column[7:0]
M
0
Bk[1:0] Row[12:0] Column[8:0]
M
0
Bk[1:0] Row[12:0] Column[9:0]
M
0
Bk[1:0] Row[12:0] Column[10:0]
M
0
32058K
AVR32-01/12